A demultiplexer 630 routes only one or more transport stream packets with a single packet identifier value to each physical layer pipe. A header compression unit 620 replaces the packet identifier of the transport stream packet with a short packet identifier of one bit length indicating at least whether the transport stream packet is a NULL packet.

A device can include interfaces configured to receive data packets from compute nodes. The device can include circuitry provide data to the compute nodes to synchronize reception of data packets received from the compute nodes. The reception can be synchronized to provide data of the data packets to each memory slot of a memory in an order.

A device can include interfaces configured to receive data packets from compute nodes. The device can include circuitry provide data to the compute nodes to synchronize reception of data packets received from the compute nodes. The reception can be synchronized to provide data of the data packets to each memory slot of a memory in an order.

Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.

Provided is a transmission circuit with which it is possible to facilitate error correction of burst errors without increasing the processing load in multiframes configured from a plurality of OTN frame signals. This transmission circuit is provided with: a transmission-side signal recognition unit for detecting MFAS and recognizing the order of N number of OTN frame signals; an intra-multiframe sequence conversion unit for converting the sequence of data signals inside the multiframe in response to the recognized order; a transmission-side rearranging unit for consolidating the sequentially converted data signals into lengths equal to those of the OTN frame signals and creating N number of quasi-OTN frame signals; and a transmission unit for transmitting the multiframes configured from the N number of quasi-OTN frame signals.

A streaming platform reader includes: a plurality of reader threads configured to retrieve messages from a plurality of partitions of a streaming platform, wherein each message in the plurality of partitions is associated with a unique identifier; a plurality of queues coupled to the plurality of reader threads configured to store messages or an end of partition signal from the reader threads, wherein each queue includes a first position that stores the earliest message stored by a queue; a writer thread controlled by gate control logic that: compares the identifiers of all of the messages in the first positions of the queues of the plurality of queues, and forwards, to a memory, the message associated with the earliest identifier; and wherein the gate control logic blocks the writer thread unless each of the queues contains a message or an end of partition signal.

A network device includes an antenna connected to an RF chip and a processor coupled to an Ethernet port, the RF chip, a program memory, a packet buffer memory, a pointer buffer memory, and a program memory. The program memory contains instruction that, when executed by the processor, cause a plurality of packets received by the antenna and the RF chip in a first order to be stored in the packet buffer memory in such order, cause a pointer associated with each one of the plurality of packets to be stored in the pointer buffer memory, cause the pointers stored in the pointer buffer memory to be placed in a second order in accordance with a timestamp that is included with each packet, cause the packets stored in the packet buffer memory to be passed along to the Ethernet port in accordance with the sorted pointer to each packet.

A processor includes a system controller configured to send predetermined packet information to a data packing and unpacking module; the data packing and unpacking module configured to acquire corresponding packet data from a storage array module according to the packet information, pack the packet data with the packet information, send a first packet obtained from packing to an operation module for operation processing, acquire a second packet returned by the operation module, unpack the second packet to obtain operation result data, and store the operation result data in the storage array module; the storage array module configured to store data; and the operation module configured to perform operation processing on the acquired first packet, generate the second packet according to the operation result data, and return the second packet to the data packing and unpacking module.

A processor includes a system controller configured to send predetermined packet information to a data packing and unpacking module; the data packing and unpacking module configured to acquire corresponding packet data from a storage array module according to the packet information, pack the packet data with the packet information, send a first packet obtained from packing to an operation module for operation processing, acquire a second packet returned by the operation module, unpack the second packet to obtain operation result data, and store the operation result data in the storage array module; the storage array module configured to store data; and the operation module configured to perform operation processing on the acquired first packet, generate the second packet according to the operation result data, and return the second packet to the data packing and unpacking module.

Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.