An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.

An interrupt processing method applied to a server including a plurality of cores, the plurality of cores include an interrupt processing core and a service processing core that runs a service process, and the method is implemented by the interrupt processing core and includes: receiving an interrupt processing request, where the interrupt processing request is used to request to process at least one of a plurality of TCP data packets of the service process that are stored in an interrupt queue, and destination ports of all of the plurality of TCP data packets correspond to a same interrupt queue; obtaining the at least one TCP data packet from the interrupt queue; determining the service processing core based on the at least one TCP data packet, where there is cache space shared by the interrupt processing core and the service processing core; and waking the service processing core.

A data transmission method for a data transmission system including a host and a peripheral device is disclosed, including: setting at least one identification number to at least one packet stored in the host; transmitting the at least one packet from the host to the peripheral device; allocating the at least one packet to plural temporary blocks of a memory of the peripheral device corresponding to the at least one identification number according to the at least one identification number of the at least one packet. Each of the temporary blocks includes a threshold value, and the threshold value of each of at least two of the temporary blocks are different; and transmitting part of the at least one packet stored in one of the temporary blocks when the one of the temporary blocks reaches the threshold value of the one of the temporary blocks.

Techniques are disclosed for using a forwarding microchip to implement a network functions virtualization (NFV) backplane within a network device. In one example, processing circuitry of a forwarding microchip establishes a respective logical connection between each of a plurality of virtual ports of the forwarding microchip and each of a plurality of virtual ports configured for respective software-implemented virtual network functions (VNFs) executing on the network device. The processing circuitry receives packets via one or more physical ports of the forwarding microchip and forwards, using the logical connections between each of the plurality of virtual ports of the forwarding microchip and each of the plurality of virtual ports configured for the respective software-implemented VNFs, the packets to a Network Interface Controller (NIC) for forwarding to the plurality of virtual ports configured for the respective software-implemented VNFs.

In one example, the present disclosure describes a device, computer-readable medium, and method for organizing terabit-scale packet volumes into flows for downstream processing stages. For instance, in one example, a method includes extracting a first flow key from a first data packet, inputting the first flow key into a hash function to obtain a first output value, selecting a first partition in a memory to which to store the first data packet, wherein the first partition is selected based on the first output value, and storing the first data packet to the first partition.

An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.

A computer-implemented method for secure data storage is described. In one embodiment, the method may include receiving data at a receiver. The method may further include integrating a storage device with the receiver, and storing the received data on the integrated storage device. The method may further include communicating the received data from the integrated storage device to be stored on a remote distributed storage network.

In one example, the present disclosure describes a device, computer-readable medium, and method for organizing terabit-scale packet volumes into flows for downstream processing stages. For instance, in one example, a method includes extracting a first flow key from a first data packet, inputting the first flow key into a hash function to obtain a first output value, selecting a first partition in a memory to which to store the first data packet, wherein the first partition is selected based on the first output value, and storing the first data packet to the first partition.

Alternate acknowledgment (ACK) signals in a coalescing Transmission Control Protocol/Internet Protocol (TCP/IP) system are disclosed. In one aspect, a network interface card (NIC) examines packet payloads, and the NIC generates an ACK signal for a sending server before sending a coalesced packet to an internal processor. Further, the NIC may examine incoming packets and send an ACK signal to the internal processor for ACK signals that are received from the sending server before sending the coalesced packet to the internal processor. By extracting and sending the ACK signals before sending the corresponding payloads in the coalesced packet, latency that would otherwise be incurred waiting for the ACK signal is eliminated. Elimination of such latency may improve network performance and may provide power savings.

A network controller being executed by a processing device generates a file descriptor indicating when the network controller or a virtual switch being executed by the processing device stored a packet to a shared memory buffer. At least one of a read or write operation being performed on the packet stored at the shared memory buffer is identified. In response to identifying the at least one of the read or write operation being performed on the packet, the file descriptor is modified in view of the at least one of the read or write operation being performed on the packet.