A method for data transmission may be implemented on an electronic device having one or more processors. The one or more processors may include a master queue including a master queue head and a plurality of primary ports that are connected to each other using a serial link. The method may include operating the master queue head to obtain a message. The method may also include operating the master queue head to segment the message into a plurality of segments. The method may also include operating the master queue head to transmit the plurality of segments to a first primary port of the plurality of primary ports in the master queue. The method may also include operating the first primary port to transmit the plurality of segments to a second primary port of the plurality of primary ports in the master queue.

At least a payload of a packet that is received by a network device is stored in a packet memory. The packet is processed at least to determine at least one egress port via which the packet is to be transmitted, modify a header of the packet to generate a modified header, and determine, based at least in part on the modified header, whether the packet is to be transmitted or to be discarded by the network device. In response to determining that the packet is to be transmitted, the at least the payload of the packet is retrieved from the packet memory, a transmit packet is generated at least by combining the at least the payload of the packet with the modified header, and the transmit packet is transmitted via the determined at least one egress port of the network device.

A network device includes a network interface for establishing a communication session with another network device, a memory to store instructions, and a processor to execute the instructions. The processor may, for each time period during the communication session, adjust a size of a receive buffer of a socket. When the processor adjusts the size, the processor, if a utilization number of the receive buffer is greater than a high threshold: may determine a first new size for the receive buffer, and set a size of the receive buffer to the first new size. If the utilization number is less than a low threshold, the processor may determine a second new size for the receive buffer; and set the size of the receive buffer to the second new size.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Embodiments of the invention include methods for handling packets in a communications network. In one embodiment, a method is implemented in an electronic device. The method includes at a first end of a queue in the electronic device, determining admission of a first packet to the first end of the queue based on a length of the first packet, where when the admission of the first packet would cause the queue to become full, the admission is further based on a packet value of the first packet and a data structure tracking packet value distribution of packets in the queue. The method further includes at a second end of the queue, dropping a second packet from the second end of the queue when the second packet's corresponding packet value is marked as to be dropped in the data structure upon admitting packets to the first end of the queue.

Packets received by a network switch device from upstream network devices, coupled to respective ones of a plurality of ports of the network switch device, are temporarily stored in an internal memory of the network switch device. In response to detecting congestion in the internal memory of the network switch device, a flow control engine triggers, during respective timeslots of a timing schedule and while the flow control engine continues to monitor congestion in the internal memory of the network switch device, transmission of respective flow control messages via different subsets of ports, among the plurality of ports, to control flow of packets from different subsets of upstream network device, among the plurality of upstream network devices, to the network switch device so that flow control is distributed over time among upstream network devices of the plurality of upstream network devices.

A packet processing method includes: a first device receives a packet from a second device; the first device determines a first queue buffer used to store the packet, and determines a first upper limit value of the first queue buffer based on an available value of a first port buffer and an available value of a global buffer, where the global buffer includes at least one port buffer, the first port buffer is one of the at least one port buffer, the first port buffer includes at least one queue buffer, and the first queue buffer is one of the at least one queue buffer. The first device processes the packet based on the first upper limit value of the first queue buffer, an occupation value of the first queue buffer, and a size of the packet.

A packet transfer device includes a circuit configured to include a first queue to store a first packet classified into a high priority class and a second queue to store a second packet classified into a low priority class, a memory configured to store data configured to indicate possibilities of output for the first packet and the second packet for each time slot, a processor coupled to the memory and configured to control the output of the first packet and the second packet for each time slot according to the data stored in the memory, count a number of discards of the second packet within the second queue in a predetermined cycle, and change the data stored in the memory, when the number of discards is less than a first predetermined value, so as to reduce an output period of the second packet every the time slot.

A method for data transmission may be implemented on an electronic device having one or more processors. The one or more processors may include a master queue including a master queue head and a plurality of primary ports that are connected to each other using a serial link. The method may include operating the master queue head to obtain a message. The method may also include operating the master queue head to segment the message into a plurality of segments. The method may also include operating the master queue head to transmit the plurality of segments to a first primary port of the plurality of primary ports in the master queue. The method may also include operating the first primary port to transmit the plurality of segments to a second primary port of the plurality of primary ports in the master queue.

A relay device accumulates received frames that are not determined as a specific frame in a queue and transfers the frames accumulated in the queue one by one according to a predetermined rule. The relay device transfers a received frame that is determined as a specific frame priority to the frames accumulated in the queue without accumulating the specific frame in the queue.