H04L49/9084

QUEUE PROTECTION USING A SHARED GLOBAL MEMORY RESERVE
20230412523 · 2023-12-21 ·

The subject technology relates to the management of a shared buffer memory in a network switch. Systems, methods, and machine readable media are provided for receiving a data packet at a first network queue from among a plurality of network queues, determining if a fill level of a queue in a shared buffer of the network switch exceeds a dynamic queue threshold, and in an event that the fill level of the shared buffer exceeds the dynamic queue threshold, determining if a fill level of the first network queue is less than a static queue minimum threshold.

STORE AND FORWARD LOGGING IN A CONTENT DELIVERY NETWORK
20230412529 · 2023-12-21 · ·

A computer-implemented method on a device. The device has hardware including storage. The method includes obtaining log event data from at least one component or service on the device that is to be delivered to a component or service on a distinct device. Each log event data item has a priority. If a connection to an external location is lost, at least some of the log event data items are selectively stored in the storage, wherein the storing is based on priority of the log event data items. Otherwise, if the connection is not lost, at least some of the log event data items are sent to the at least one external location.

HIERARCHICAL STATISTICALLY MULTIPLEXED COUNTERS AND A METHOD THEREOF

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

Congestion avoidance in a network switch device
10917349 · 2021-02-09 · ·

Packets received by a network switch device from upstream network devices, coupled to respective ones of a plurality of ports of the network switch device, are temporarily stored in an internal memory of the network switch device. In response to detecting a first congestion state in the internal memory, the network switch device transmits a first flow control message via a first subset of ports, without transmitting the flow control message via any port not included in the first subset of ports, to cause upstream network devices in a first subset of upstream network devices to temporarily suspend transmission of packets to the network switch device. The network switch device alternates between causing different subsets of the network devices to temporarily suspend transmission of packets to the network switch device, while continuing to monitor congestion in the internal memory of the network switch device.

Network interface device that sets an ECN-CE bit in response to detecting congestion at an internal bus interface

A network device includes a Network Interface Device (NID) and multiple servers. Each server is coupled to the NID via a corresponding PCIe bus. The NID has a network port through which it receives packets. The packets are destined for one of the servers. The NID detects a PCIe congestion condition regarding the PCIe bus to the server. Rather than transferring the packet across the bus, the NID buffers the packet and places a pointer to the packet in an overflow queue. If the level of bus congestion is high, the NID sets the packet's ECN-CE bit. When PCIe bus congestion subsides, the packet passes to the server. The server responds by returning an ACK whose ECE bit is set. The originating TCP endpoint in turn reduces the rate at which it sends data to the destination server, thereby reducing congestion at the PCIe bus interface within the network device.

CONTROLLING SOCKET RECEIVE BUFFER FOR TRAFFIC OPTIMIZATION
20210075744 · 2021-03-11 ·

A network device includes a network interface for establishing a communication session with another network device, a memory to store instructions, and a processor to execute the instructions. The processor may, for each time period during the communication session, adjust a size of a receive buffer of a socket. When the processor adjusts the size, the processor, if a utilization number of the receive buffer is greater than a high threshold: may determine a first new size for the receive buffer, and set a size of the receive buffer to the first new size. If the utilization number is less than a low threshold, the processor may determine a second new size for the receive buffer; and set the size of the receive buffer to the second new size.

ELECTRONIC CONTROL UNIT, ABNORMALITY DETERMINATION PROGRAM, AND ABNORMALITY DETERMINATION METHOD
20210036971 · 2021-02-04 ·

An electronic control unit includes a receiver that receives a data frame transmitted at given transmission periods from a transmission source electronic control unit connected via a communication network, a buffer capable of storing the data frame, a writer that writes the data frame received by the receiver into the buffer, and an abnormality determiner that determines that the data frame is abnormal when the number of data frames written into the buffer exceeds a given threshold or when the data frame is written in excess of a capacity of the buffer.

NETWORK PACKET RECEIVING APPARATUS AND METHOD

A network packet receiving device that includes packet queues, a credit allocation circuit and a credit management circuit is provided. Each of the packet queues corresponds to a packet transmission channel and receives packets. The credit allocation circuit calculates packet amount of each of the packet queues to control the descriptor credit of each of the packet queues within a credit range. The credit management circuit points each of public entries of a public link list to one of descriptors in a single descriptor buffer. The credit management circuit further receives a credit requesting command from the packet queues to assign the descriptors to the packet queues through the public entries under the condition that the descriptor credit is within a credit range such that a DMA circuit performs a DMA operation on the packets according to the descriptors.

PACKET FRAGMENT PROCESSING METHOD AND APPARATUS AND SYSTEM
20210014179 · 2021-01-14 ·

This application provides a packet fragment processing method and apparatus and a system, to reduce occupancy of a storage resource of a network device. The method includes: receiving, by a network device, a first packet fragment set from first user equipment, where the first packet fragment set includes a plurality of packet fragments; and sending, by the network device, the first packet fragment set to a server.

Dynamic Offline End-to-End Packet Processing based on Traffic Class
20200412655 · 2020-12-31 ·

Methods and apparatus for dynamic offline end-to-end packet processing based on traffic class. An end-to-end connection is set up between an application on a client including a processor and host memory and an application on a remote server. An offline packet buffer is allocated in host memory. While the processor and/or a core on with the client application is executed is in a sleep state, the client is operated in an interrupt-less and polling-less mode as applied to a predetermined traffic class. Under the mode, a Network Interface Controller (NIC) at the client receives network traffic from the remote server and determines whether the network traffic is associated with the predetermined traffic class. When it is, the NIC writes packet data extracted from the network traffic to an offline packet buffer. Descriptors are generated and provided to the NIC to inform the NIC of the location and size of the offline packet buffer.