Systems, apparatuses, and methods are provided for fast format-preserving encryption. An input string can be divided into blocks (potentially of varying length). An arrangement of cryptographic pipelines can perform operations on different blocks, each pipeline providing an output block. The cryptographic pipelines can interact such that the output blocks are dependent on each other, thereby providing strong encryption. The pipelines can operate efficiently on the block and operations can occur partly in parallel.

A trust relationship may be established between a host system and a storage system. An asymmetric key pair including a private key unique to a host system and a public key may be generated. During provisioning of the host system to the storage system, the host system may send the public key to the storage system. The storage system may be configured to record the public key for the host system, for example, in a masking table that defines I/O connectivity for logical storage units between a host system and the storage system. The public key may be used later to validate the host system to the storage system. The private key may be stored on the host system and be unreadable, or may be encrypted with an unreadable encryption key stored on the host system.

A system and method for providing a rapid, yet highly secure cryptographic application, to provide enhanced protection for digital data. At least one random value and Deterministic Sequence Generator (DSG) seeds are mathematically processed to create an initialization value (IV). The initialization value (IV) is mathematically processed with a user key to generate a set of initial DSG vectors. The initial DSG vectors are then inputted into a DGS component, and, using the initial DSG vectors, the DSG component creates an additive table and a substitution table. An initial internal working key is generated from the user key and the initial DSG vectors. An addition, an XOR and a substitution operation is applied to each byte of plaintext data in combination with the internal working key to enable the cipher to quickly and effectively encrypt the plaintext data. Once encrypted, the encrypted data may be stored in memory for subsequent use and/or transmitted to another party. Decryption of the encrypted data may be performed by applying the inverse of the above process.

Systems and methods for protecting block cipher computation operations from external monitoring attacks. An example apparatus for implementing a block cipher may comprise a memory device to store instructions for computing a block cipher; and a processing device coupled to the memory device. The processing device performs a Data Encryption Standard (DES) cryptographic operation with multiple rounds of a Feistel structure, each round including a substitution function and a transformation function that combines an expansion function and a permutation function into a single operation. The transformation function transforms a first input portion of an internal state of the respective round and a second input portion of the internal state into a first output portion and a second output portion of data. The second output portion is equal to the first input portion and the first output portion is dependent on a combined permutation output from the transformation function.

A processor device has an executable implementation of a cryptographic algorithm implemented thereon, which algorithm is adapted to produce an output text from an input text employing a secret key K. The implementation of the algorithm comprises a key-dependent computing step S which comprises a key combination of input values x derived directly or indirectly from the input text with key values SubK derived directly or indirectly from the key; the key-dependent computing step S is represented by a table which is masked with input masking and/or output masking to form a masked table TabSSubK; and a new masked table TabSKneu is generated in the processor device.

In various embodiments, a computer-readable memory medium coupled to a processor is disclosed. The memory medium is configured to store instructions which cause the processor to retrieve a seed value, receive a digital bit stream, receive a digital bit stream, generate a stream of random bits, using the seed value as a seed to a pseudo random number generator (PRNG), wherein the stream of random bits contains at least as many bits as the digital bit stream, shuffle bits of the stream of random bits to create a random bit buffer, generate an obfuscated digital bit stream by applying a first exclusive OR (XOR) to the digital bit stream and the random bit buffer, wherein the obfuscated digital bit stream has the same number of bits as the digital bit stream, and provide the obfuscated digital bit stream to the communications interface.

An integrated circuit includes functional circuitry such as a processing core, memory interfaces, cryptographic circuitry, etc. The integrated circuit also includes protection circuitry to protect the functional circuitry of the integrated circuit against attacks by hidden channels. The protection circuitry, for each of a series of successive periods of time, selects a configuration of the functional circuitry from a set of configurations of the functional circuitry, sets a duration of the period of time, and applies the selected configuration of the functional circuitry for the set duration of the period of time.

In various embodiments, a computer-readable memory medium coupled to a processor is disclosed. The memory medium is configured to store instructions which cause the processor to retrieve a seed value, receive a digital bit stream, receive a digital bit stream, generate a stream of random bits, using the seed value as a seed to a pseudo random number generator (PRNG), wherein the stream of random bits contains at least as many bits as the digital bit stream, shuffle bits of the stream of random bits to create a random bit buffer, generate an obfuscated digital bit stream by applying a first exclusive OR (XOR) to the digital bit stream and the random bit buffer, wherein the obfuscated digital bit stream has the same number of bits as the digital bit stream, and provide the obfuscated digital bit stream to the communications interface.

The present disclosure relates to the exchange of information between a message sending device and a message receiving device with message authentication and proposes to reduce the time required for message authentication by pre-computing a message tag, such as a MAC, and subsequently replacing the computation of the MAC when the tag is to be validated (or indeed also on sending) by a table look-up. The approach requires a set of messages and works particularly well for small sets of messages, for example as small as two or three messages, or less than five or ten messages. The approach finds particular application in control networks where control decisions have to be taken quickly and securely, for example in the control of a vehicle, for example an autonomous vehicle, or the control of a smart electricity grid.

A method of producing a white-box implementation of a cryptographic function, including: creating, by a processor, a white-box implementation of a cryptographic function using a network of two dimensional lookup tables; identifying two dimensional lookup tables using a common index; and rewriting the identified two dimensional lookup tables as a three dimensional table.