Patent classifications
H04L2209/125
ROBUST STATE SYNCHRONIZATION FOR STATEFUL HASH-BASED SIGNATURES
In one example an apparatus comprises a computer readable memory, a signing facility comprising a plurality of hardware security modules, and a state synchronization manager comprising processing circuitry to select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module, and assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence. Other examples may be described.
PARALLEL BLOCK PROCESSING IN BLOCKCHAINS
Certain aspects of the present disclosure provide techniques for reporting transactions in a blockchain. The method generally includes instantiating a plurality of worker processes for processing blocks from a blockchain in parallel. Each worker process is generally associated with an offset into a buffer of blocks from the blockchain to be reported to one or more computing resources. A subject block to be reported to the one or more computing resources is selected from the buffer. The subject block is generally a block inserted into the buffer by a worker process. The subject block is validated based on a block number associated with the subject block and a block number of a next block to be reported. Based on validating the subject block, the subject block is reported to the one or more computing resources, and the subject block is marked in the buffer as a reported block.
Command-type filtering based on per-command filtering indicator
An adjunct processor dynamically determines, on a per-command basis, whether commands obtained by the adjunct processor are to be processed by the adjunct processor. The adjunct processor obtains a command request of a requester. The command request includes at least one filtering indicator indicating at least one valid command type for processing by the adjunct processor for the requester. The adjunct processor determines using the at least one filtering indicator whether a command of the command request is valid for processing by the adjunct processor for the requester. Based on determining that the command is valid for processing by the adjunct processor, the command is processed by the adjunct processor.
SYSTEM AND METHOD FOR PROVIDING SHARED HASH ENGINES ARCHITECTURE FOR A BITCOIN BLOCK CHAIN
A method and system for sharing hash calculations across N parallel mining threads, the method comprising: finding N Merkle root hash values that have identical marginal portions of a predetermined size, calculating a corresponding mid-state hash for each of the N Merkle root hash values, and transmitting the N Merkle root hash values along with the corresponding mid-state values to the N parallel mining threads.
METHOD AND SYSTEM FOR REDUCING POWER CONSUMPTION IN BITCOIN MINING VIA DATA INPUT HOPPING
A method and engine for hash calculation, the method comprising receiving data blocks via an input module, providing clock cycles by a clock module, calculating a hash from a received data block by a process module including a data pipeline and a state pipeline, the hash calculation comprising: receiving an input data block to the data pipeline, calculating, in every other clock cycle of the clock module, an induced data block based on the previous data block, and performing a stage of the state pipeline in each clock cycle of the clock module, in which a state is calculated based on input from the data pipeline, and outputting the hash via an output module.
SECURE HASH ALGORITHM IN DIGITAL HARDWARE FOR CRYPTOGRAPHIC APPLICATIONS
Technology, implemented in digital hardware, software, or combination thereof, for completing Secure Hash Algorithm (SHA-2) computation with generating one new hash value at each clock cycle is described. The technology includes: using synchronous logic to store the computed values every alternate clock and combinational logic to process multiple rounds of SHA in each clock; completing hash calculation in unrolled modes; using efficient adders for most 32-bit adders to improve performance.
Systems and methods for implementing robotics frameworks
Systems, methods, and non-transitory computer-readable media can receive a message transmitted over a robotics framework implemented on a vehicle. A determination can be made that the message satisfies criteria for multi-threaded hashing. The message can be divided into two or more message segments. A hash can be independently computed for each message segment of the two or more message segments to generate two or more message segment hashes. A message hash can be determined for the message based on the two or more message segment hashes.
DATA ENCRYPTION
In some examples, applying a first encryption process to input data blocks for encrypted data blocks, applying a deduplication process to the encrypted data blocks for chunks and first hashes, applying a deduplication process to the hashes for a first set of deduplicated hashes and sending it to destination computer. If there are missing data blocks at the computer based on the first set of deduplicated hashes: receiving a second set of deduplicated hashes of the missing data blocks, selecting chunks from the input data blocks of the missing data blocks from the second set of deduplicated hashes, applying a second encryption process to selected chunks for encrypted data chunks, and applying a third encryption process to the first hashes for first encrypted hashes.
POWER SIDE-CHANNEL ATTACK RESISTANT ADVANCED ENCRYPTION STANDARD ACCELERATOR PROCESSOR
A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a random number generator to generate a byte order indicator. The hardware accelerator also includes a first switching module communicatively coupled to the random value indicator generator. The switching module receives an byte sequence in an encryption round of the cryptographic operation and feeds a portion of the input byte sequence to one of a first substitute box (S-box) module or a second S-box module in view of a byte order indicator value generated by the random number generator.
METHOD AND SYSTEM FOR REDUCING POWER CONSUMPTION IN BITCOIN MINING VIA WATERFALL STRUCTURE
A method and engine for hash calculation, the method comprising receiving data blocks via an input module, providing clock cycles by a clock module, calculating a hash from a received data block by a process module including a data pipeline and a state pipeline, the hash calculation comprising: an input data block to the data pipeline, the data block includes a sequence of data words including X data words, wherein X is a known number, calculating, in every other clock cycle of the clock module, an new data word based on the last calculated X data words, and performing a stage of the state pipeline in each clock cycle of the clock module, in which a state is calculated based on input from the data pipeline, the input includes the last calculated X data words, and outputting the hash via an output module every predetermined number of clock cycles.