Embodiments of this application provide a control method based on a vertical synchronization signal and an electronic device, to shorten a response delay of the electronic device and improve fluency of the electronic device without increasing load of the electronic device. The method may include: drawing, by an electronic device including a display screen, one or more layers in response to a first vertical synchronization signal; refreshing and displaying an image frame in response to a second vertical synchronization signal; adjusting the first vertical synchronization signal, so that the adjusted first vertical synchronization signal is delayed by first delay time relative to the second vertical synchronization signal; and drawing one or more layers in response to the adjusted first vertical synchronization signal.

Systems and methods enable rendering picture-in-picture (PIP) video outputs and re-rendering of the rendered video file to remove particular excluded video elements and/or add selectively included elements independently from other video elements. Input video data is analyzed for the presence of presentation elements and the portions of the video including the presentation element are tracked in an event log. A PIP output video is rendered that includes the presentation element. Upon receiving a command to exclude the presentation element, the portions of the PIP output video containing the presentation element are re-rendered to remove the presentation element from the PIP output video.

Systems and methods enable rendering picture-in-picture (PIP) video outputs and re-rendering of the rendered video file to remove particular excluded video elements and/or add selectively included elements independently from other video elements. Input video data is analyzed for the presence of presentation elements and the portions of the video including the presentation element are tracked in an event log. A PIP output video is rendered that includes the presentation element. Upon receiving a command to exclude the presentation element, the portions of the PIP output video containing the presentation element are re-rendered to remove the presentation element from the PIP output video.

The methods described herein are configured to correlate frames of a video stream to a system clock. A correlator application receives a frame of a video stream from a capture device via a bus interface, the frame including start frame and end frame timestamps based on a device clock of the capture device. A second start frame timestamp and second end frame timestamp are predicted based on previously received frames and a system clock. A skew value of the frame is calculated based on differences between the start frame timestamps and the end frame timestamps. Upon the calculated skew value exceeding a skew threshold, the frame is corrected to correlate to the predicted start frame and end frame timestamps. The corrected frame is then provided for display. Correcting timestamps of video stream frames in the described manner reduces jitter and enables accurate synchronization of multiple video streams.

The methods described herein are configured to correlate frames of a video stream to a system clock. A correlator application receives a frame of a video stream from a capture device via a bus interface, the frame including start frame and end frame timestamps based on a device clock of the capture device. A second start frame timestamp and second end frame timestamp are predicted based on previously received frames and a system clock. A skew value of the frame is calculated based on differences between the start frame timestamps and the end frame timestamps. Upon the calculated skew value exceeding a skew threshold, the frame is corrected to correlate to the predicted start frame and end frame timestamps. The corrected frame is then provided for display. Correcting timestamps of video stream frames in the described manner reduces jitter and enables accurate synchronization of multiple video streams.

A method minimizes audio and video streaming delays between a video source and a video sink. A receiver receives a netsync message from a transmitter that communicates with the video source to receive input video. The netsync message is generated by the transmitter in accordance with the input video and indicates a display pointer of the transmitter. In accordance with the netsync message, the receiver adaptively outputs a set of timing control signals that is transmitted to the video sink, thereby minimizing the latency between the vertical synchronization (VSYNC) of the transmitter and the VSYNC of the receiver.

A method minimizes audio and video streaming delays between a video source and a video sink. A receiver receives a netsync message from a transmitter that communicates with the video source to receive input video. The netsync message is generated by the transmitter in accordance with the input video and indicates a display pointer of the transmitter. In accordance with the netsync message, the receiver adaptively outputs a set of timing control signals that is transmitted to the video sink, thereby minimizing the latency between the vertical synchronization (VSYNC) of the transmitter and the VSYNC of the receiver.

An image processing method includes: combining a padding region with a picture, wherein any padding pixel included in the padding region is assigned with a predetermined pixel value; and encoding the picture having the padding region combined therewith. For example, the padding region is directly below a bottom edge of the picture. For another example, all of padding pixels included in the padding region have the same pixel value.

A reconfigurable pin-to-pin interface includes lane circuits and a reconfiguration circuit. A first lane circuit of the lane circuits obtains a first received signal by receiving a first input signal transmitted via a first lane. A second lane circuit of the lane circuits obtains a second received signal by receiving a second input signal transmitted via a second lane. When the second lane is used as one data lane and the first lane is used as one clock lane, the reconfiguration circuit redirects the first received signal to the second lane circuit for acting as an clock input of the second lane circuit. When the first lane is used as one data lane, the reconfiguration circuit blocks the first received signal from being redirected to the second lane circuit for acting as the clock input of the second lane circuit.

A reconfigurable pin-to-pin interface includes lane circuits and a reconfiguration circuit. A first lane circuit of the lane circuits obtains a first received signal by receiving a first input signal transmitted via a first lane. A second lane circuit of the lane circuits obtains a second received signal by receiving a second input signal transmitted via a second lane. When the second lane is used as one data lane and the first lane is used as one clock lane, the reconfiguration circuit redirects the first received signal to the second lane circuit for acting as an clock input of the second lane circuit. When the first lane is used as one data lane, the reconfiguration circuit blocks the first received signal from being redirected to the second lane circuit for acting as the clock input of the second lane circuit.