A receiving device for reducing video latency includes a display render unit, a communication interface, a memory, and a processor. The display render unit performs a video transmission to output a video to a display apparatus. The video generated by a video capture unit of the sending device is transmitted through the communication interface to the receiving device. The memory stores at least one computer readable instruction. The processor accesses and executes the at least one computer readable instruction to: determine whether a video latency is necessary to be reduced; determine a target reduced latency based on a target line count and a current line count; and determine a first period based on the target reduced latency and an accelerating scheme at the display render unit. The display render unit performs the video transmission to the display apparatus based on the accelerating scheme for the first period.

A semiconductor device including an image sensor device controlled by an adjusting circuit, and the adjusting circuit configured to transmit a control signal to the image sensor device to be controlled according to a transmission cycle synchronized with a reference clock, the image sensor device includes a first period during which the control signal is allowed to be supplied to the image sensor device to be controlled and a second period during which the supplying of the control signal to the image sensor device to be controlled is not preferable compared to that in the first period, the adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period to the image sensor device.

A semiconductor device including an image sensor device controlled by an adjusting circuit, and the adjusting circuit configured to transmit a control signal to the image sensor device to be controlled according to a transmission cycle synchronized with a reference clock, the image sensor device includes a first period during which the control signal is allowed to be supplied to the image sensor device to be controlled and a second period during which the supplying of the control signal to the image sensor device to be controlled is not preferable compared to that in the first period, the adjusting circuit is configured to, when a transmission timing of the control signal determined according to the transmission cycle is within the second period, adjust the transmission timing of the control signal so that the control signal will be transmitted in the first period to the image sensor device.

Focal plane distortion is prevented from standing out in the vicinity of a joint when a plurality of captured images are stitched and synthesized. A plurality of cameras are provided. Each camera includes an image sensor that outputs a signal by a raster scan scheme. Phases of a vertical synchronization signal supplied to the image sensors of the plurality of cameras are respectively shifted according to information of gap amounts of captured images of the respective cameras from a reference position in a vertical direction. Even if there are gaps in the vertical direction between the installed cameras, positional gaps between the installed image sensors due to variations in individual camera main bodies, and the like, there are no lines with largely different capture times in the vicinity of a joint of a synthesized image, and focal plane distortion is prevented from standing out in the vicinity of this joint.

Focal plane distortion is prevented from standing out in the vicinity of a joint when a plurality of captured images are stitched and synthesized. A plurality of cameras are provided. Each camera includes an image sensor that outputs a signal by a raster scan scheme. Phases of a vertical synchronization signal supplied to the image sensors of the plurality of cameras are respectively shifted according to information of gap amounts of captured images of the respective cameras from a reference position in a vertical direction. Even if there are gaps in the vertical direction between the installed cameras, positional gaps between the installed image sensors due to variations in individual camera main bodies, and the like, there are no lines with largely different capture times in the vicinity of a joint of a synthesized image, and focal plane distortion is prevented from standing out in the vicinity of this joint.

A control device includes: generation circuitry configured to output a field signal to a medical imaging device; first detection circuitry configured to detect a horizontal synchronization signal from video data output from the medical imaging device, the video data including at least the horizontal synchronization signal; and a monitoring circuitry configured to monitor whether or not an abnormality occurs in one frame period of the video data based on a period of the horizontal synchronization signal detected by the first detection circuitry for a predetermined n-th time after polarity of the field signal is switched.

A control device includes: generation circuitry configured to output a field signal to a medical imaging device; first detection circuitry configured to detect a horizontal synchronization signal from video data output from the medical imaging device, the video data including at least the horizontal synchronization signal; and a monitoring circuitry configured to monitor whether or not an abnormality occurs in one frame period of the video data based on a period of the horizontal synchronization signal detected by the first detection circuitry for a predetermined n-th time after polarity of the field signal is switched.

A synchronization signal generation function of an image transmitter is configured to generate an imaging synchronization signal. One or more processors of the image transmitter cause an imager of the image transmitter to perform new imaging every time the imaging synchronization signal is generated and cause communication data corresponding to captured image data output from the imager to be transmitted from a communicator of the image transmitter to an image receiver by radio waves. A synchronization signal generation function of the image receiver is configured to generate a display synchronization signal. One or more processors of the image receiver is configured to generate a display image corresponding to the captured image data from the communication data received by radio waves in a communicator of the image receiver and cause a monitor of the image receiver to display a newly generated display image every time the display synchronization signal is generated.

A synchronization signal generation function of an image transmitter is configured to generate an imaging synchronization signal. One or more processors of the image transmitter cause an imager of the image transmitter to perform new imaging every time the imaging synchronization signal is generated and cause communication data corresponding to captured image data output from the imager to be transmitted from a communicator of the image transmitter to an image receiver by radio waves. A synchronization signal generation function of the image receiver is configured to generate a display synchronization signal. One or more processors of the image receiver is configured to generate a display image corresponding to the captured image data from the communication data received by radio waves in a communicator of the image receiver and cause a monitor of the image receiver to display a newly generated display image every time the display synchronization signal is generated.

Provided is a video processing device that generates a display video signal to be supplied to a liquid crystal display having a liquid crystal that is driven by a frame inversion scheme and includes a control microcomputer and a video signal processor. The control microcomputer controls a data enable signal such that a display invalid section having a predetermined number of fields is set for an interlace video signal at a predetermined period based on a vertical synchronization signal included in the interlace video signal input from outside. The video signal processor generates the display video signal by setting the display invalid section for the interlace video signal based on the data enable signal and outputs the display video signal to the liquid crystal display.