A data transmitting and receiving device includes: a data transmitting circuit transmitting a clock signal and a data signal synchronized to the clock signal; and a data receiving circuit receiving the clock signal and the data signal; wherein: the data receiving circuit includes a phase error detection circuit detecting a phase error between the data signal and the clock signal; and the data transmitting circuit includes a phase adjusting circuit adjusting a phase of at least one of the clock signal and the data signal based on the phase error.

Provided is a video processing device that generates a display video signal to be supplied to a liquid crystal display having a liquid crystal that is driven by a frame inversion scheme and includes a control microcomputer and a video signal processor. The control microcomputer controls a data enable signal such that a display invalid section having a predetermined number of fields is set for an interlace video signal at a predetermined period based on a vertical synchronization signal included in the interlace video signal input from outside. The video signal processor generates the display video signal by setting the display invalid section for the interlace video signal based on the data enable signal and outputs the display video signal to the liquid crystal display.

A high-speed video system is disclosed that includes a moving image absorbing disk at an image plane. The disk has a pattern that passes and blocks image data. The disk is located between an event and an image sensor, or reflects an image to the image sensor. The disk is rotated at a speed that matches the desired reconstructed image frame rate. The image sensor frame data is processed using image reconstruction techniques, such as the D-AMP or TWIST algorithm, to recover a time sequence of reconstructed images. Additional images can be reconstructed for each image sensor frame if some spatial resolution is sacrificed. For continuous video, the disk speed is adjusted to the sensor frame rate. For burst mode, a single sensor image is acquired and a short image sequence is reconstructed. This image capture system works with a variety of radiations, including infrared, light, UV and X-rays.

A source driving device includes a locking module, a controlling module and a decoding module. The locking module executes a locking process selectively in a first band or a second band according to a band setting signal in order to lock a first clock signal synchronized with a first display signal. The controlling module is coupled to the locking module for comparing a control voltage with a reference voltage in the locking process and generates the band setting signal accordingly. The decoding module is coupled to the locking module for generating a decoded signal according to the first display signal and the first clock signal.

Disclosed are a controlling device and method for frequency synchronization as well as a LCD TV. The method is applied to an LCD TV, wherein the LCD TV includes a front-end motherboard chip, a main drive control chip and a plurality of column drive control chips, the method includes: when the main drive control chip recognizes that its operating frequency is unstable, it generates a clock turn-off signal; the main drive control chip transmits fixed data to each column drive control chip according to the clock turn-off signal and receives a clock training request initiated by each column drive control chip according to the fixed data; and when recognizing that the operating frequency synchronizes with a frequency corresponding to front-end data transmitted by the front-end motherboard chip, the main drive control chip responds to the clock training request and transmits clock training data to each column drive control chip.

An image output synchronization method, performed by a programmable logic circuit connected to an oscillator, includes: configuring a count value according to a designated frame rate and a frequency of the oscillator generating a count signal by each one of a plurality of frame controllers; generating a synchronization signal periodically and outputting the synchronization signal to the frame controllers by a clock generator; and performing a synchronization procedure on a camera by each one of the frame controllers when triggered by the synchronization signal every time, with the synchronization procedure including: triggered by the count signal of the oscillator to control a frame control signal outputted to the camera according to the count value and a width of the count signal.