In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing, section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-convert d are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

Provided in the present invention are techniques for processing video. The techniques comprise: converting, by a transmitting end, video data into at least one video data frame at a first framerate; transmitting, by the transmitting end, a frame generated within a previous frame duration to a receiving end for one time only within each frame duration corresponding to the first frame rate, wherein a ratio of a transmission time of each frame to a transmission cycle is less than or equal to 1:2, wherein the transmission cycle is approximately equal to a frame duration corresponding to the first frame rate; receiving, by the receiving end, two respective frames within two adjacent frame durations corresponding to the first frame rate; performing operation processing on the received frames; and combining the processed frames into a set of frames to be played back.

Provided in the present invention are techniques for processing video data. The video data processing techniques comprise: converting, by a transmitting end, video data into at least one video data frame at a first framerate; transmitting, by the transmitting end, a same frame generated within a previous frame duration at least twice to the receiving end within each frame duration corresponding to the first frame rate; receiving, by the receiving end, two different frames within two adjacent frame durations respectively, wherein the adjacent two frames each correspond to the first frame rate; performing frame insertion operation on the received frames; inserting a frame between the received frames and forming a set of frames to be played back.

In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

A video processor chip includes a memory circuit, a frame rate converter circuit, and an image compensation circuit. The memory circuit includes first to third storage spaces. The frame rate converter circuit sequentially writes multiple frame data in video data to the first to the third storage spaces respectively, and reads second data in the frame data from the memory circuit to perform a frame rate conversion when first data in the frame data is written to the memory circuit. The second data is a previous frame data of the first data. The image compensation circuit reads third data in the frame data from the memory circuit when the frame rate converter circuit reads the second data, and performs an image compensation according to a difference between the second data and the third data. The third data is a previous frame data of the second data.

A wireless transmission controller device is proposed. The device includes: a signal transmitter configured to receive an image signal input from a USB Type-C or a DP port, which are connected to an image storage device, convert the received image signal into a form of a high-speed serial signal, and wirelessly transmits the converted image signal to a signal receiver by ultra-high frequency communication; and the signal receiver configured to receive a high-speed serial signal from the signal transmitter, undergo a conversion process, and transmit the image signal to an image display device such as a monitor or a smartphone connected to the DP port, wherein, through making the USB Type-C or the Display Port to be wireless, high-speed wireless transmission in real time for a video is possible without a wired cable connection.

In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

Display control device 100 in the present invention includes: memory 101 that stores an image signal input from a signal source; controller 102 that determines the number of output frames based on an input vertical synchronizing signal input from the signal source, the output frames being frames to be displayed on a display in one cycle of the input vertical synchronizing signal, and that determines a dot number in an output horizontal period such that a gap between an output frame line number of a predetermined output frame and the output frame line number of a different output frame in a period corresponding to one cycle of the input vertical synchronizing signal is smaller than a predetermined threshold, the output horizontal period being one cycle of an output horizontal synchronizing signal, the output frame line number being the number of output horizontal periods corresponding to the output frame; and output section 103 that reads the image signal from storage 101 depending on the dot number determined by controller 102, and that outputs the read image signal on the display.

In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed. In a reproducing state, raw data are read from the recording device 111 at a low screen rate according to a display performance of the display section 112 and the raw data that have been read are processed are processed by the pre-processing circuit 202 and the camera signal processing circuit 203 and a reproduced image is displayed by the display section 112.

A video output apparatus that outputs video data in a first format to a conversion apparatus that converts and outputs the received data in the first format into data in a second format. The conversion apparatus sequentially outputs a blank signal, a vertical synchronization signal, and a blank signal. The video output apparatus includes a frame image data output unit that outputs the first frame image data to the conversion apparatus, a blank signal output unit that outputs a blank signal to the conversion apparatus, and a trigger signal output unit that outputs, to the conversion apparatus, a trigger signal to be converted into a vertical synchronization signal by the conversion apparatus.