An image decoding method supporting a plurality of layers according to the present invention may comprise the steps of: generating an inter-layer reference picture set with respect to one or more reference layers to which a current picture can refer; generating an initial reference picture list including the inter-layer reference picture set; and predicting the current picture on the basis of the initial reference picture list. Accordingly, the present invention provides a method for generating a reference picture list including a picture of a layer, which is different from a layer to be currently encoded and decoded, and an apparatus using the same.

Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pipeline may be prefetched from memory. Prefetches for the motion vectors may be initiated one or more stages prior to a processing stage. Cache tags for the cache may be defined by the motion vectors. When a motion vector is received, the tags can be checked to determine if there are cache block(s) corresponding to the vector (cache hits) in the cache. Upon a cache miss, a cache block in the cache is selected according to a replacement policy, the respective tag is updated, and a prefetch (e.g., via DMA) for the respective reference data is issued.

A video coding device, comprising a sequence of filters that are configurable by one or more primary parameters and one or more secondary parameters, and a filter controller configured to adjust the one or more secondary parameters based on the one or more primary parameters and based on a strength criterion of the sequence of filters.

Using the techniques discussed herein, a set of images is captured by one or more array imagers (106). Each array imager includes multiple imagers configured in various manners. Each array imager captures multiple images of substantially a same scene at substantially a same time. The images captured by each array image are encoded by multiple processors (112, 114). Each processor can encode sets of images captured by a different array imager, or each processor can encode different sets of images captured by the same array imager. The encoding of the images is performed using various image-compression techniques so that the information that results from the encoding is smaller, in terms of storage size, than the uncompressed images.

An apparatus includes a memory and a hardware pipeline. The memory may be configured to store video data. The video data includes a plurality of sections of one or more pictures that may be processed independently. The hardware pipeline comprises a plurality of pipeline stages implementing a video coding process comprising a number of steps. Each of the plurality of pipeline stages performs an associated task of a different step of the video coding process in a substantially similar time on a different one of the plurality of sections as each of the plurality of sections pass through each of the pipeline stages. At least one of the plurality of pipeline stages communicates predictor information that is based on actual neighbor data to an earlier stage of the hardware pipeline.

Reconstructing a video signal based on low-complexity DST7 design including obtaining a transform index of a current block from the video signal and deriving a transform combination corresponding to the transform index. The transform index corresponds to any one of a plurality of transform combinations including a combination of DST7 and/or DCT8, and the transform combination includes horizontal and vertical transforms that correspond to at least one of the DST7 or the DCT8. The reconstruction also includes performing an inverse transform in a vertical direction by using the DST7, performing an inverse transform in a horizontal direction by using the DCT8, and reconstructing the video signal by using the current block on which the inverse transform is performed. The DST7 includes Discrete Fourier Transform (DFT) and has a different type of DFT structure based on a size of the current block.

Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU or CPU. The apparatus may divide a current frame of a plurality of frames into a plurality of blocks. The apparatus may also generate an encoding value representing data for each of the plurality of blocks in the current frame. Further, the apparatus may compare the encoding value representing the data for each block in the current frame with a previous encoding value representing previous data for a corresponding block in a previous frame. The apparatus may also store the data for at least one block in the current frame if the encoding value representing the data for the at least one block is not similar to the previous encoding value representing the previous data for at least one corresponding block in the previous frame.

A technique is described herein for temporally and spatially interpolating input video information, to produce output video information having a higher frame rate and a higher resolution compared to that exhibited by the input video information. The technique generates feature information based on plural frames of the input video information. The technique then produces the output video information based on the feature information using an architecture having, in order, a multi-stage encoding operation, a query-generating operation, and a multi-stage decoding operation. Each encoding stage produces an instance of encoder attention information that expresses identified relations across the plural frames of the input video information. Each decoding stage operates on an instance of encoder attention information produced by a corresponding encoding stage. The transformer architecture is compact and is capable of interpolating the input video information in real time.

Aspects of the disclosure provide methods and an apparatus including processing circuitry that decodes coded information of a coding block (CB) in a picture from a coded video bitstream. The coded information indicates a width W and a height H of the CB. The processing circuitry partitions the CB into sub-processing units (SPUs) having a width being a minimum one of W and K and a height being a minimum one of H and K. At least one of the width W and the height H is larger than a processing data unit size K. The processing circuitry determines a partitioning structure to partition the SPUs based on the width, the height, and a maximum transform unit (TU) size M. At least one of the width and the height is larger than M. The processing circuitry partitions each of the SPUs into TUs of M×M based on the partitioning structure.

Using the techniques discussed herein, a set of images is captured by one or more array imagers (106). Each array imager includes multiple imagers configured in various manners. Each array imager captures multiple images of substantially a same scene at substantially a same time. The images captured by each array image are encoded by multiple processors (112, 114). Each processor can encode sets of images captured by a different array imager, or each processor can encode different sets of images captured by the same array imager. The encoding of the images is performed using various image-compression techniques so that the information that results from the encoding is smaller, in terms of storage size, than the uncompressed images.