An imaging device with an arithmetic function in which the circuit size is reduced is provided. The imaging device includes a plurality of pixel blocks. Each of the pixel blocks includes N (N is an integer greater than or equal to 1) first circuits, N second circuits, and a third circuit. Each of the first circuits includes a photoelectric conversion device, and the photoelectric conversion device has a function of converting incident light into an electrical signal and has a function of outputting a first signal that is obtained by binarizing the electrical signal to the second circuit. Each of the second circuits has a function of outputting a second signal that is obtained by multiplying the first signal by a weight coefficient to a third circuit. When the N second signals are output to a wiring electrically connected to the third circuit, addition is performed. The first circuit includes a transistor, and an OS transistor is preferably used as the transistor.

Technologies are described herein for an eye tracking that may be employed by devices and systems such as head mount display (HMD) devices. Light that is reflected from a user's eye may be specular or scattered. The specular light has an intensity or magnitude that may saturate the electronics. The presently disclosed techniques mitigate saturation by generating detected signals from an optical detector, evaluating the signal levels for the detected signal, and selectively gating the detected signals that have saturated. The remaining scattered signals can be combined to achieve a combined signal that can be converted into a digital signal without saturating the electronics, which can then be processed to form an image of the eye for identification purposes, for tracking eye movement, and for other uses. The described technologies provide a clear image without ambient light reflections or specular light interfering with the image.

The pixel region includes a first phase difference pixel group including a plurality of the phase difference pixels of which the first side of the photoelectric conversion element is blocked by the light blocking layer in a first side region of the first side, and a second phase difference pixel group including a plurality of the phase difference pixels of which the second side of the photoelectric conversion element is blocked by the light blocking layer. The first phase difference pixel group includes a first A pixel and a first B pixel in which a light blocking area of the photoelectric conversion element using the light blocking layer is smaller than that of the first A pixel. The controller performs addition readout processing in which at least one of a pixel signal of the first A pixel or a pixel signal of the first B pixel is weighted in accordance with optical characteristics of the imaging lens.

An image sensor includes a plurality of pixels configured to receive an optical signal incident through a first lens portion; a planarization layer that has a same refractive index as a refractive index of the first lens portion; a second lens portion that is configured to classify the optical signal incident through the first lens portion according to an incidence angle, and is configured to deliver the optical signal to each of the plurality of pixels; and image processing circuitry configured to generate a subject image by combining one or more subimages obtained from the optical signal, wherein the planarization layer is arranged between the second lens portion and the plurality of pixels.

Power consumption in realizing a convolutional neural network (CNN) is reduced.

A solid-state imaging element according to the present technology includes a photoelectric conversion element that photoelectrically converts received light into signal charge corresponding to the amount of received light, a floating diffusion that holds the signal charge obtained by the photoelectric conversion element, a transfer control element that controls transfer of the signal charge from the photoelectric conversion element to the floating diffusion, and a control unit that controls application of a drive voltage to the transfer control element on the basis of a convolution coefficient in a CNN.

A semiconductor apparatus includes a stack of first and second chips each having a plurality of pixel circuits arranged in a matrix form. The pixel circuit of the a-th row and the e1-th column is connected to the electric circuit of the p-th row and the v-th column. The pixel circuit of the a-th row and the f1-th column is connected to the electric circuit of the q-th row and the v-th column. The pixel circuit of the a-th row and the g1-th column is connected to the electric circuit of the r-th row and the v-th column. The pixel circuit of the a-th row and the h1-th column is connected to the electric circuit of the s-th row and the v-th column.

Techniques are described for disparity-preserving pixel binning during consistently binned parallel readout of an imaging sensor array having both phase detection autofocus (PDAF) pixels and imaging pixels. Each group of PDAF pixels and each group of imaging pixels is coupled with pixel actuators according to an particular arrangement, so that consistently applied control of the pixel actuators results in desired binning of both the PDAF pixels and the imaging pixels. According to some implementations, though such control of the pixel actuators is consistently applied across the pixels of the array, parallel readout of the sensor array yields diagonally binned imaging pixels, but vertically binned PDAF pixels to preserve horizontal PDAF disparity information. Additionally or alternatively, disparity-inducing structures are configured to position same-disparity PDAF pixels so that consistently applied control of the pixel actuators preserves disparity information during binning.

A system for dark current compensation in SPAD imagery is configurable to capture an image frame with the SPAD array and generate a temporally filtered image by performing a temporal filtering operation using the image frame and at least one preceding image frame. The at least one preceding image frame is captured by the SPAD array at a timepoint that temporally precedes a timepoint associated with the image frame. The system is also configurable to obtain a dark current image frame. The dark current image frame includes data indicating one or more SPAD pixels of the plurality of SPAD pixels that detect an avalanche event without detecting a corresponding photon. The system is also configurable to generate a dark current compensated image by performing a subtraction operation on the temporally filtered image or the image frame based on the dark current image frame.

An image sensor includes a plurality of red pixel groups, a first red pixel and a second red pixel adjacent to each other in a first direction; a plurality of green pixel groups, a first green pixel and a second green pixel adjacent to each other in the first direction; a plurality of blue pixel groups, a first blue pixel and a second blue pixel adjacent to each other in the first direction; and at least one color pixel group including a first color pixel and a second color pixel each configured to sense a certain color, the first color pixel and the second color pixel adjacent to each other in a second direction, the at least one color pixel group being between the red pixel groups and the green pixel groups and between the green pixel groups and the blue pixel groups.

In a pixel 200, a floating diffusion FD11 and a first capacitor CS11 are selectively connected to each other via a first connection element LG11-Tr, to change the capacitance of the floating diffusion FD11 between a first capacitance and a second capacitance, thereby changing the conversion gain between a first conversion gain (HCG) corresponding to the first capacitance and a second conversion gain (MCG) corresponding to the second capacitance. The floating diffusion FD11 and a second capacitor CS12 are connected together through a second connection element SG11-Tr to change the capacitance of the floating diffusion FD11 to a third capacitance, thereby changing the conversion gain of the source following transistor SF11-Tr to a third conversion gain (LCG) corresponding to the third capacitance