An image sensor includes: a plurality of pixels having photoelectric conversion units that convert incident light to charges, and readout units; a first signal line, connected to the plurality of pixels, that outputs a first signal transferred to the readout unit based upon the charge converted by the photoelectric conversion unit; and a second signal line, connected to the plurality of pixels, that outputs a second signal after the readout unit has been reset.

The present technology relates to a signal processing device, an image pickup element, and an electronic device capable of suppressing power source variation due to driving of a counter. The signal processing device according to the present technology includes a first A/D converter which performs A/D conversion on an analog signal by using a first counter being a predetermined counter and a second A/D converter which performs the A/D conversion on the analog signal by using a second counter count timing of which is the same as that of the first counter and a polarity of a count value of which is opposite to that of the first counter. The first and second A/D converters are arranged in the vicinity of each other such that power source variations thereof affect both. The present technology may be applied to the image pickup element and the electronic device, for example.

A digital X-ray detector is provided. The digital X-ray detector includes control circuitry. The control circuitry is configured to obtain an electromagnetic interference (EMI) frequency of an EMI signal, to receive a signal to start a scan, to ensure EMI noise is in a same phase during acquisition of offset images and read images to enable a subtraction of the EMI noise, and to start the scan.

Techniques are described for controlling operation of a pixel conversion ADC in a manner that enforces strict timing and synchronization of ramp and clock signaling. Synchronizing techniques can be applied to generate a corrected ramp start signal based on synchronizing a received ramp start signal to an input clocking signal, and to generate a controller clock signal based on synchronizing an input clocking signal to the corrected ramp start signal. The corrected ramp start signal and the controller clock signal can be used to control generation of a ramp enable signal for controlling timing of pixel ramp voltage generation digital pixel conversion counting, and to control generation of an output clocking signal used by the digital pixel conversion counting.

A clock control circuit of an ADC includes a plurality of fractional divider circuits, each including a programmable integer divider coupled to receive an enable skew signal, a clock signal, and an output integer signal to divide down the clock signal by a factor responsive to the output integer signal to generate a fractional divider signal. A delta-sigma modulator is coupled to receive a fractional modulus signal, an input integer signal, and the fractional divider signal to generate the output integer signal, which is a varying signal each cycle and having a long term average DC value substantially equal to a fractional divider ratio K. An extended gain control circuit is coupled to receive the fractional divider signal from each of the fractional divider circuits to generate a plurality of ramp clock signals with adjustable frequencies to adjust a gain setting of a ramp generator of the ADC.

An image sensor includes a first amplifier comparing and amplifying a first voltage signal received from a first column line, and a ramp signal; a second amplifier amplifying an output of the first amplifier; a third amplifier comparing and amplifying a second voltage signal received from a second column line, and the ramp signal; and a fourth amplifier amplifying an output of the third amplifier, wherein the second amplifier and the fourth amplifier output a decision signal at different points in time by dummy switch control split.

The present disclosure relates to a solid-state imaging device, an AD converter, and an electronic apparatus that improve a crosstalk characteristic. The AD converter includes a comparator that compares the pixel signal with the reference signal, a pixel signal side capacitor, and a reference signal side capacitor. The pixel signal side capacitor and the reference signal side capacitor are formed such that a first parasitic capacity, and a second parasitic capacity are substantially the same. The present technology is applicable to a CMOS image sensor, for example.

A solid-state imaging device including a semiconductor substrate; plural photoelectric conversion units formed side by side on the semiconductor substrate to form a light receiving unit; a peripheral circuit formed in a portion on an outside of the light receiving unit on the semiconductor substrate; a wiring section formed on the light receiving unit and formed for connecting the plural photoelectric conversion units and the peripheral circuit; and a dummy wiring section formed on an opposite side of the wiring section for at least one photoelectric conversion unit among the plural photoelectric conversion units on the light receiving unit and formed for functioning as a non-connected wiring section not connected to the photoelectric conversion units and the peripheral circuit, wherein the dummy wiring section has a predetermined potential.

In an electronic device that employs high-speed differential signaling on one or more pairs of conductors in a flexible printed circuit, RF chokes are placed in the differential signal path and mounted directly on the flexible printed circuit which is used to interconnect a peripheral device, such as an image sensor, through a connector to another device component such as a main printed circuit board. The RF chokes are configured to suppress common-mode noise propagating in the differential pairs of conductors. In one illustrative embodiment, the RF chokes are located on the flexible printed circuit adjacent to the peripheral device to suppress common-mode noise near its source. In another illustrative embodiment, the RF chokes are mounted adjacent to the connector to suppress the common-mode noise before it has an opportunity to escape the flexible printed circuit at the major discontinuity presented by the connector.

A solid-state imaging element includes a pixel section including a plurality of pixels that are arranged in a matrix and to perform photoelectric conversion, and circuitry to perform reading control on pixels in the pixel section, such that reading control is not performed on at least one pixel included in the pixel section.