There is provided an imaging device capable of suppressing an occurrence of shading in any input image at any shutter timing when the fine shutter is implemented without restriction on the exposure time.

The imaging device includes a shutter function capable of performing a shutter operation at a desired timing within one horizontal synchronization period, in which in a pixel layout configuration in which pixels each including a photoelectric conversion unit are disposed in a matrix shape, a pixel control line is wired for each pixel row with respect to a matrix-like pixel array, and a vertical signal line and a power supply line of a high-potential-side power supply voltage are wired for each pixel column in a wiring layer different from a wiring layer in which the pixel control line is wired, the vertical signal line is shielded by a shielding power supply line of a low-potential-side power supply voltage.

An electronic device and a control method are provided. The electronic device includes a sensing pixel. The sensing pixel includes a photosensitive element, a first transistor, a second transistor and a third transistor. The first transistor is coupled to the photosensitive element and for receiving a reset signal. The second transistor is coupled to the photosensitive element. The third transistor is coupled to the second transistor and for receiving a scan signal. During a reset period, a reset signal waveform of the reset signal and a first scan signal waveform of the scan signal are at least partially overlapped.

A pixel circuit, a driving method thereof, an array substrate, and a display device are provided. The pixel circuit includes signal inputting sub-circuit, signal reading sub-circuit, and photosensitive element. The signal inputting sub-circuit is configured to: under control of inputting control terminal, turn on coupling between signal inputting terminal and first terminal of photosensitive element in signal writing period, and turn off coupling between signal inputting terminal and first terminal of photosensitive element in exposure period and signal reading period. The signal reading sub-circuit is configured to: under control of reading control terminal, turn off coupling between first terminal of photosensitive element and signal reading terminal in signal writing period and exposure period, and turn on coupling between first terminal of photosensitive element and signal reading terminal in signal reading period. Second terminal of photosensitive element is coupled to common electrode signal inputting terminal.

An electronic circuit includes a unit pixel, a first clamp circuit, and a second clamp circuit. The unit pixel outputs a voltage having an output voltage level at a first output voltage level in a first time interval and at a second output voltage level in a second time interval different from the first time interval. The first clamp circuit is configured to clamp the output voltage level from the unit pixel to a first voltage level responsive to the first output voltage level being not greater than the first voltage level in the first time interval. The second clamp circuit is configured to clamp the output voltage level from the unit pixel to a second voltage level responsive to the second output voltage level being not greater than the second voltage level in the second time interval.

An imaging device includes a pixel and a signal processor configured to apply a first set of control signals to the pixel to generate a first pixel signal, a second pixel signal, a third pixel signal, and a fourth pixel signal based on light reflected from an object. The signal processor is configured to apply a second set of control signals to the pixel to generate a fifth pixel signal, a sixth pixel signal, a seventh pixel signal, and an eighth pixel signal based on the light reflected from the object. The signal processor is configured to calculate a distance to the object based on comparisons between selected ones of the first, second, third, fourth, fifth, sixth, seventh, and eighth pixel signals.

An image sensing device includes a first substrate configured to include a plurality of unit pixels configured to detect incident light to produce pixel signals carrying image information in the incident light, a second substrate positioned adjacent to the first substrate and including a structure that generates a first magnetic field at the first substrate affecting the plurality of unit pixels and at least one shielding device disposed between the first substrate and the second substrate, wherein the shielding device includes a sensing circuit configured to detect a first voltage corresponding to the first magnetic field and an offset circuit configured to generate, based on the first voltage, a second magnetic field that counteracts the first magnetic field.

A communication module includes a first wiring board including a plurality of first signal lines and a first ground line, and a second wiring board including a first layer and a second layer. The first layer includes a plurality of second signal lines. The second layer includes a shielding member. The communication module includes a plurality of first connection members via which the plurality of first signal lines are electrically connected to the plurality of second signal lines, and at least one conductive member provided between the first ground line and the shielding member. The at least one conductive member is provided so as to overlap with at least one second signal line among the plurality of second signal lines as viewed in a direction perpendicular to a main surface of the first wiring board.

An image sensor includes pixel regions separated by an isolation region and receiving incident light, color filters respectively disposed on a surface of the semiconductor substrate corresponding to the pixel regions, a cover insulating layer disposed on the surface of the semiconductor substrate and covering the color filters, first transparent electrodes disposed on the cover insulating layer and spaced apart to respectively overlap the color filters, an isolation pattern disposed on the cover insulating layer between the first transparent electrodes and having a trench spaced apart from the first transparent electrodes, a drain electrode disposed in the trench of the isolation pattern, and an organic photoelectric layer and a second transparent electrode sequentially disposed on the first transparent electrodes and the isolation pattern.

Techniques are described for controlling operation of a pixel conversion ADC in a manner that enforces strict timing and synchronization of ramp and clock signaling. Synchronizing techniques can be applied to generate a corrected ramp start signal based on synchronizing a received ramp start signal to an input clocking signal, and to generate a controller clock signal based on synchronizing an input clocking signal to the corrected ramp start signal. The corrected ramp start signal and the controller clock signal can be used to control generation of a ramp enable signal for controlling timing of pixel ramp voltage generation digital pixel conversion counting, and to control generation of an output clocking signal used by the digital pixel conversion counting.

An image sensor including a pixel array section in which a plurality of pixels including photoelectric conversion units is disposed, and a comparator that compares an analog pixel signal output from the pixels to a predetermined reference signal, and outputs a comparison result according to a signal level of the pixel signal. The comparator includes differential pair transistors, a first load transistor connected in series with a first transistor of the differential pair, and a second load transistor connected in series with a second transistor of the differential pair. The first transistor of the differential pair accepts a signal obtained by combining the pixel signal and the predetermined reference signal as a gate input, the second transistor of the differential pair accepts a predetermined voltage as a gate input. In addition, a capacitance unit is connected between a common connection node of the first transistor of the differential pair and the first load transistor, and a node of the predetermined voltage.