The present technology relates to a solid-state imaging device, an electronic apparatus, and an AD converter that are capable of suppressing the occurrence of an error in AD conversion results. The solid-state imaging device includes a pixel section having a plurality of pixels, a comparator for comparing a pixel signal outputted from the pixels with a reference signal, and a counter for counting the time of comparison made by the comparator. The comparator includes a first amplifier for comparing the pixel signal with the reference signal, a second amplifier that has a first transistor and amplifies an output signal of the first amplifier, and a second transistor having the same polarity as the first transistor. A gate of the second transistor is connected to an output end of the first amplifier, and a source and a drain of the second transistor are connected to the same fixed potential as a source of the first transistor. The present technology is applicable, for example, to a CMOS image sensor.

In a photoelectric changing unit, a photoelectric conversion unit converts light into electric charge, and an electric charge accumulation unit accumulates the electric charge in a polygonal area whose plurality of sides are adjacent to the photoelectric conversion unit on a light receiving surface. A voltage generation unit accumulates the electric charge and generates a voltage according to an amount of the accumulated electric charge. A first transfer unit transfers the electric charge from the photoelectric conversion unit to the electric charge accumulation unit when an instruction on a transfer to the electric charge accumulation unit is issued. A second transfer unit transfers the electric charge from the electric charge accumulation unit to the voltage generation unit when an instruction on a transfer to the voltage generation unit is issued.

A method of reducing noise in an image sensor using a parallel multi-ramps merged comparator analog-to-digital converter (ADC) starts with a pixel array capturing image data. The pixel array includes pixels to generate pixel data signals, respectively. An ADC circuitry acquires the pixel data signals. The ADC circuitry includes ADC circuits. Each of the ADC circuits includes a comparator and latches. The comparator includes a multi-input first stage. The comparator in each ADC circuit compares one of the pixel data signals to ramp signals received from a logic circuitry to generate comparator output signals. The latches in each ADC circuit latches the counter based on the comparator output signals, respectively, to generate ADC outputs. Other embodiments are described.

The disclosure provides a receiver with reduced noise. The receiver includes a photodiode that generates an input signal in response to received light pulses. A pixel switch is coupled to the photodiode. An operational amplifier is coupled to the photodiode through the pixel switch. A feedback capacitor and a reset switch are coupled between a first input port and an output port of the operational amplifier. A switched resistor network is coupled to the output port of the operational amplifier. A first switched capacitor network is coupled to the switched resistor network and samples a reset voltage. A second switched capacitor network is coupled to the switched resistor network and samples a signal voltage. A subtractor receives the reset voltage and the signal voltage, and generates a sample voltage. The second switched network comprises two or more capacitors.

An example apparatus for random sampling for horizontal noise reduction includes readout circuitry coupled to receive image data from an array of pixels, the readout circuitry including a plurality of sample and hold (S&H) circuits coupled to respective ones of a plurality of bitlines to sample and hold the image data in response to a plurality of S&H control signals, each of the plurality of S&H circuits including an S&H capacitor and an S&H switch. The S&H capacitor samples and holds respective image data, and the S&H switch coupled between a respective bitline and to the respective S&H capacitor, and further coupled to receive a respective one of the plurality of S&H control signals to open/close the S&H switch, where each of the plurality of S&H switches are opened to decouple their respective S&H capacitors from the respective bitlines at a different.

Noise of signals in an image sensor is reduced. A pixel circuit generates a reset signal of a predetermined initial voltage and an exposure signal of a signal voltage according to an exposure amount of light in order. An analog-digital conversion unit performs a reset sampling process of converting the reset signal into a first digital signal at a predetermined reset sampling interval and an exposure sampling process of converting the exposure signal into a second digital signal at an exposure sampling interval that does not exceed twice the predetermined reset sampling interval in order. A detection unit detects the light based on the first digital signal and a second digital signal.

An imaging apparatus includes an imaging device, a readout unit, and a correction unit. The readout unit performs a first reading operation of reading out a first signal corresponding to accumulated electric charge on a pixel included in a first area of the imaging device, and performs a second reading operation of reading out a second signal corresponding to accumulated electric charge on a pixel included in a second area different from the first area. The correction unit corrects image signals based on signals obtained from the first and second areas by use of neighboring image signals obtained from neighboring pixels located near a pixel targeted for the correction process, and coefficients corresponding respectively to the neighboring pixels. The correction unit sets a coefficient corresponding to each of the neighboring pixels in accordance with the first or second reading operation executed on a neighboring pixel of the neighboring pixels.

Provided is an imaging device that performs multiple AD conversions including a first AD conversion and a second AD conversion for one pixel signal. A first memory has a bit width of N+1 bits (N is a natural number) and holds the least significant bit to the N+1th bit of a digital value obtained by the first AD conversion, and second memory has a bit width of M bits (M is a natural number) greater than N+1 bits and holds the least significant bit to the Mth bit of a digital value obtained by the second AD conversion.

The present technology relates to an imaging device that can reduce the size thereof, and to an electronic apparatus.

An upper substrate and a lower substrate are stacked. A pixel and a comparing unit that compares the voltage of a signal from the pixel with the ramp voltage are provided on the upper substrate, the ramp voltage varying with time. A storage unit that stores a code value obtained at a time when a comparison result from the comparing unit is inverted is provided on the lower substrate. The comparing unit is formed with a transistor that receives the voltage of the signal from the pixel at the gate, receives the ramp voltage at the source, and outputs a drain voltage. Accordingly, the imaging device can be made smaller in size. The present technology can be applied to image sensors.

An iris recognition system may include an optical system having an intentional amount of spherical aberration that results in an extended depth of field. A raw image of an iris captured by the optical system may be normalized. In some embodiments, the normalized raw image may be processed to enhance the MTF of the normalized iris image. An iris code may be generated from the normalized raw image or the enhanced normalized raw image. The iris code may be compared to known iris codes to determine if there is a match.