A TFT layer is provided that includes a stack of, in sequence, display wires, a protective film, a first flattening film, a metal wire layer and a second flattening film; further, a frame region has a first trench and a second trench respectively provided in the first flattening film and the second flattening film and overlapping the display wires; further, a second electrode is provided to cover the first trench and the second trench; further the protective film includes a first protective film and a third protective film formed of a silicon oxide film, and a second protective film formed of a silicon nitride film.

A plurality of inner protrusions are provided in a non-display area so as to surround a through hole. Each of the plurality of inner protrusions includes: an underlying resin layer; and an underlying inorganic insulation layer provided on the underlying resin layer. Each underlying resin layer is separated by a plurality of inner slits formed on a surface of a resin substrate layer so as to surround the through hole. The underlying inorganic insulation layer is provided so as to project like an eave from the underlying resin layer to either one or both of a through hole side and a display area side.

A display device includes: a base substrate; a thin-film transistor layer provided on the base substrate and having a stack of, in sequence, a lower wire, a flattening film composed of an organic insulating film, an interlayer insulating film composed of an inorganic insulating film, and an upper wire; and a light-emitting element layer, wherein the flattening film has a first contact hole formed to pass through the flattening film and formed for electrically connecting the lower wire and the upper wire together, the interlayer insulating film has a second contact hole formed to pass through the interlayer insulating film and formed for electrically connecting the lower wire and the upper wire together, and at least a part at an edge of the flattening film provided with the first contact hole is exposed from an edge of the interlayer insulating film provided with the second contact hole.

A barrier film for electronic devices exhibiting and maintaining excellent water barrier property. The barrier film for electronic devices features a water permeability (23° C., RH50%) that is set to be not more than 10.sup.−4 g/m.sup.2/day and a water content that is maintained to be not more than 2000 ppm.

Provided is a display device that can retard the degradation of light-emitting elements even when the display device is used in a high temperature environment. A display device includes a TFT layer, a light-emitting element layer provided with a plurality of light-emitting elements, a heat dissipating layer, an extraction member, and a thermal insulation layer that insulates the light-emitting elements from external heat. The thermal insulation layer is made from a material containing a first resin in which a metal complex compound having an ammonium salt as a ligand is dispersed. The TFT layer is formed between the heat dissipating layer and the light-emitting element layer. The heat dissipating layer overlaps the light-emitting elements. The thermal insulation layer surrounds the heat dissipating layer. The extraction member is formed to overlap the thermal insulation layer. The heat dissipating layer and the thermal insulation layer are in direct contact with the TFT layer.

An organic EL display device has a frame region provided with a first dam wall and a second dam wall to surround a display region. The first dam wall and the second dam wall include: a first resin wall layer; a first conductive wall layer covering the first resin wall layer; a second resin wall layer over the first resin wall layer through the first conductive wall layer; and a second conductive wall layer covering the second resin wall layer. The second resin wall layer is positioned between: a step portion included in the first conductive wall layer and covering a peripheral end face of the first resin wall layer; and a portion included in the second conductive wall layer and corresponding to the step portion of the first conductive wall layer.

An organic EL display device includes an organic EL element disposed on a flattening film, and a sealing film disposed over the organic EL element, a display region, and a frame region disposed around the display region. The frame region includes a plurality of mask spacers. The flattening film has a recess disposed between the display region and the mask spacers adjacent to the display region. The recess is filled with an organic film.

A display device includes a base member, a thin film transistor, an organic insulation film, a light-emitting layer, and a sealing layer. The display device has an active area and a non-active area. The non-active area includes a notched portion and a protrusion portion surrounding the notched portion and having, on a notched portion side, a side face including a reverse-tapered face. The light-emitting layer is disconnected as a result of a step at the protrusion portion. A filling material is embedded in at least a part of a space located between the reverse-tapered face and a top face of the organic insulation film. The top face overlaps the reverse-tapered face in a plan view.

A light emitting device includes: a substrate; a light emitting region including light emitting elements arranged in a matrix on the substrate; and a sealing portion located on the light emitting region. A single lens covering the light emitting region is formed in the sealing portion. Furthermore, a method for manufacturing a light emitting device includes: a step of forming a light emitting region including light emitting elements arranged in a matrix on a substrate; and a step of performing sealing by forming a single lens covering the light emitting region.

The present invention overcomes image defects such as the brightness inclination or smears by reducing the line resistance of a power source bus line which supplies electricity to organic EL elements. A plurality of pixels which are arranged in a matrix array is connected to power source lines, and the plurality of power source lines are connected to a power source bus line. Both ends of the power source bus line are connected to a power source part via a FPC. By supplying electricity to both ends of the power source bus line from the power source part, the line resistance of the power source bus line can be reduced.