The present application provides a method and device of managing materials. In processes of manufacturing display devices, circuit board identifiers of flexible circuit boards and panel identifiers of display panels are obtained, and then the circuit board identifiers are bound with the panel identifiers. In a later stage, material management is performed on the display panels according to the circuit board identifiers. Based on the circuit board identifiers, sources of the display panels can be traced, so that no industrial inkjet printers are required and thus costs of material management can be reduced.

A flexible circuit board includes a flexible light-permeable carrier, a circuit layer, a mark and a stiffener. The circuit layer and the mark are located on a top surface of the flexible light-permeable carrier. A predetermined area and a stiffener mounting area corresponding to each other are defined on the top surface and a bottom surface of the flexible light-permeable carrier, respectively. The mark is opaque to create a shadow mark having a longitudinal reference side and a lateral reference side on the bottom surface. The stiffener is adhered to the stiffener mounting area defined on the bottom surface by aligning with the longitudinal reference side and the lateral reference side of the shadow mark.

An apparatus includes a printed circuit board (PCB) that includes a woven glass laminate layer. The woven glass laminate layer includes a plurality of glass bundles woven together, where a marker structure including at least one marker is defined within the woven glass laminate layer. A security chip is coupled with the PCB and includes memory that stores an authentication identifier of the PCB, where the authentication ID includes a representation of the marker structure.

The display device comprises a first base portion including display and non-display areas and a pad area, and a printed circuit film attached to the pad area of the first base portion, wherein pad electrodes on the first base portion and a first panel alignment mark on one side of the plurality of pad electrodes are disposed in the pad area, a first protective layer is on the pad electrodes, and a first open portion that exposes a portion of an upper surface of each pad electrode is defined in the protective layer, the printed circuit film includes a third base portion and lead electrodes on a lower surface of the third base portion and connected to the pad electrodes, and the first panel alignment mark includes a first panel alignment metal portion and a second open portion and surrounded by the first panel alignment metal portion on a plane.

In a method for producing a wiring circuit board, a conductive pattern is formed using a plating resist formed by photolithography for sequentially moving one photomask in a first direction with respect to a dry film resist to be exposed a plurality of times. The conductive pattern has a conductive intermediate portion which is inclined. The one photomask has a third photo pattern. The third photo pattern includes a first photoline pattern and a second photo line pattern. A first portion of the first photoline pattern coincides with a second portion of the second photoline pattern when projected in the first direction.

A wiring circuit board includes an alignment mark layer. The alignment mark layer includes a first alignment mark and a second alignment mark. The condition A or the condition B is satisfied. Condition A: The first alignment mark has a first portion (a first starting point portion or a first center of gravity portion). The second alignment mark has a second portion (a second starting point portion or a second center of gravity portion). Condition B: The first alignment mark has the first portion, and the second alignment mark does not have the second portion, or the first alignment mark does not have the first portion, and the second alignment mark does not have the second portion.

In the invention described, a method of creating a unique tag or labeling system for electronic printed circuit board assemblies (PCBA) that is unique, virtually un-duplicatable, and may be altered when the electronics are tampered with.

A method for manufacturing an integrated multilayer structure includes obtaining a substrate film having first and second sides, providing at least on the first side one or more first functional features, arranging at least one layer upon at least the first side; removing, at least a portion of the substrate film so that space is released in the structure wherein a detachment-enhancing feature provided to the substrate film is configured to facilitate the removal of the at least a portion of the substrate film such that the adjacent remaining film material, if any, the arranged layer and the one or more first functional features are preserved and preferably remain substantially intact; and providing at least one second functional feature into the space released for use so that the at least one second functional feature operatively connects with at least one of the one or more first functional features.

An identification circuit (10) for identifying one circuit board (30) among a plurality of circuit boards (30) includes a switching element (11) that switches the one circuit board (30) electrically connected to the identification circuit (10) among the plurality of circuit boards (30), a circuit element group (12) electrically connected to the switching element (11), and a controller (13) electrically connected to the switching element (11) and the circuit element group (12). Upon an identification resistor (Ri) and/or an identification capacitor (Ci) being electrically connected to the circuit element group (12) via the switching element (11), the controller (13) measures a determination time (T), which is different for each circuit board (10), based on the connected identification resistor (Ri) and/or the connected identification capacitor (Ci) and identifies the one circuit board (30) based on the measured determination time (T).

A wiring circuit board includes an insulating layer, a wire embedded in the insulating layer, and an alignment mark electrically independent from the wire and disposed in the insulating layer so as to allow a one-side surface in a thickness direction of the alignment mark to be exposed from the insulating layer. A peripheral portion of the alignment mark consists of only the insulating layer and has a thickness of 30 μm or less.