A mini smart card and a method of manufacturing the mini smart card are introduced. The method includes disposing bilayered print layers on a top side and a bottom side of a circuit layer, respectively; performing a heat-compression treatment and then a printing treatment on the circuit layer and the bilayered print layers; removing surface layers from the bilayered print layers; and disposing transparent protective layers on the bilayered print layers, respectively. The bilayered print layers are prevented from deforming under the heat generated during the printing treatment. Removal of the surface layers from the bilayered print layers effectively reduces the thickness of the mini smart card.

A semiconductor device including a semiconductor chip disposed on a substrate having a conductive pattern, an insulating plate and a metal plate that are sequentially formed and respectively have the thicknesses of T2, T1 and T3. The metal plate has a plurality of depressions formed on a rear surface thereof. In a side view, a first edge face, which is an edge face of the conductive pattern, is at a first distance away from a second edge face that is an edge face of the metal plate, and a third edge face, which is an edge face of the semiconductor chip, is at a second distance away from the second edge face. Each depression is located within a depression formation distance from the first edge face, where: 0<depression formation distance≤(0.9×T1.sup.2/first distance), and/or (1.1×T1.sup.2/first distance)≤depression formation distance<second distance.

The present application provides an asymmetric board, which includes the first master board, the second master board, and the insulating dielectric layer sandwiched between the first master board and the second master board, and the depth control grooves are disposed in the connection position between the units on the asymmetric board, and located on the surface of the second master board and extending a toward the side of the first master board, the depth control grooves provide space for the expansion of the second master board, reduce the stress of the units, and reduce the warping of the second master board. When the number of the depth control grooves in the first direction and/or the second direction is greater than 0, the depths of the depth control grooves increase by X from a center to an edge of the asymmetric board, and the X is greater than or equal to 0.

The casing of an electronic control device includes a casing-side contact surface in contact with the end of a printed-circuit board. A cover includes a cover-side contact surface holding the end of the printed-circuit board together with the casing-side contact surface by being in contact with the end of the printed-circuit board. In the printed-circuit board, a held portion held between the casing-side contact surface and the cover-side contact surface is provided with a through-hole via.

An electronic component includes an electronic element and an interposer board. The electronic element includes a multilayer body and external electrodes each at a respective one of multilayer body end surfaces of the multilayer body and connected to internal electrode layers. The interposer board includes board end surfaces, board side surfaces orthogonal to the board end surfaces, and board main surfaces orthogonal to the board end surface and the board side surface. One of the board main surfaces is located in a vicinity of the electronic element and joined with one of multilayer body main surfaces in a vicinity of the interposer board. The interposer board is an alumina board. The external electrodes each include a first Sn plated layer that covers an outer surface of the interposer board in a vicinity of at least one board end surface.

An electronic component includes an electronic element and an interposer board. The electronic element includes a multilayer body and external electrodes at multilayer body end surfaces of the multilayer body and connected to internal electrode layers. The interposer board includes board end surfaces, board side surfaces orthogonal to the board end surfaces, and board main surfaces orthogonal to the board end surface and the board side surface. One of the board main surfaces is located in a vicinity of the electronic element and joined with one of the pair of multilayer body main surfaces in the vicinity of the board. The interposer board is an alumina board. The board end surfaces each include a metal layer including a Zn-containing layer and a Cu layer on an outer periphery of the Zn-containing layer.

A wiring substrate includes an insulating layer including resin and filler particles, conductor layers including an upper-layer conductor layer and a lower-layer conductor layer such that the insulating layer is sandwiched between the upper-layer and lower-layer conductor layers, and a penetrating conductor formed in the insulating layer such that the penetrating conductor is penetrating through the insulating layer and connecting the upper-layer and lower-layer conductor layers. The penetrating conductor is formed such that the penetrating conductor has a first length which is the maximum width of the penetrating conductor in the direction orthogonal to the thickness direction of the wiring substrate and the first length is 25 μm or less, and the insulating layer is formed such that the maximum particle size of the filler particles in a region within the distance of 40% of the first length from the penetrating conductor is 20% or less of the first length.

An electronic component includes an electronic element and an interposer board. The electronic element includes a multilayer body and external electrodes at multilayer body end surfaces and connected to internal electrode layers. The interposer board includes board end surfaces, board side surfaces orthogonal to the board end surfaces, and board main surfaces orthogonal to the board end surfaces and the board side surfaces. One of the board main surfaces is in a vicinity of the electronic element and is joined with one of the multilayer body main surfaces in a vicinity of the interposer board. The interposer board is an alumina board. A maximum length of the interposer board is smaller than a length of the electronic element. A width of the interposer board is smaller than a width of the electronic element.

A glass circuit board includes, on a glass substrate, a stress relief layer, a seed layer, and an electroplated layer including copper plating. The stress relief layer is an insulator formed by dry coating method and applies a compressive residual stress to the glass substrate at room temperature. The stress relief layer thus reduces cracking, fracturing or warpage of the glass substrate caused by thermal expansion and shrinkage of the copper plating due to heating and cooling of the glass circuit board during manufacturing or thermal cycling, ensuring high connection reliability of the glass circuit board.

A glass wiring board that can be kept from cracking by better preventing concentration of stresses in a glass plate on which a conductor layer including an electrolytic copper plating layer is provided, the wiring board includes: a glass plate; a first metal layer covering at least a part of the glass plate; and a second metal layer covering at least a part of the first metal layer, and the area of the first metal layer in contact with the second metal layer is smaller than the area of the second metal layer facing the first metal layer.