Tamper-proof electronic packages and fabrication methods are provided including an enclosure enclosing, at least in part, at least one electronic component within a secure volume, a two-phase dielectric fluid within the secure volume, and a tamper-respondent detector. The tamper-respondent detector monitors, at least in part, temperature and pressure of the two-phase dielectric fluid. In operation, the two-phase dielectric fluid deviates from an established saturation line of the two-phase dielectric fluid within the secure volume with an intrusion event into the secure volume, and the tamper-respondent detector detects, from the monitoring of the temperature and pressure of the two-phase dielectric fluid, the deviation from the established saturation line, and thereby occurrence of the intrusion event.

A self-protecting electronic circuit may include an energetic substrate comprising an energetic material, a plurality of traces disposed onto the energetic substrate, and at least one surface component couple to the plurality of trace. The self-protecting electronic circuit may optionally include a non-platable insulator disposed on portion of the energetic substrate not having the plurality of traced disposed thereon. The at least one surface component may include an activation mechanism for initiating the energetic substrate. Methods for making a self-protecting electronic circuit include forming an energetic substrate, coating the energetic substrate with an insulator, removing at least a portion of the insulator from the energetic substrate, and disposing at least one trace onto the energetic substrate.

Provided is a method for masking a sensitive signal by injecting noise into planes of a printed circuit board (PCB). The method comprises detecting, by a secondary integrated circuit (IC), a noise signal on a shared plane of a PCB that includes the secondary IC. The noise signal may be analyzed to determine the characteristics of the noise signal. A masking signal may be generated based on the characteristics. The masking signal may then be injected onto the shared plane.

A hybrid transaction card reader system includes a hybrid transaction card reader and a device for protecting the hybrid reader. The hybrid transaction card reader includes a magnetic strip reader and a chip reader. The device for protecting the hybrid reader includes an upper protective printed circuit and a lower protective printed circuit. The hybrid reader further includes a lateral protective printed circuit which includes a superposition of unitary printed circuits, the plane of superposition of the unitary printed circuits being parallel to the plane of the upper protective printed circuit and to the plane of the lower protective printed circuit.

An anti-tamper assembly is disclosed for a circuit board which comprises one or more electronic components. The assembly comprises a container having side walls, a first closed end and a second, opposing open end, the container being configured to be mounted on said circuit board at said open end, over at least one of the electronic components to form, in use, a sealed cavity around said at least one of said electronic components. The assembly further comprises a source of radioactive particles mounted within the container, an image sensor for capturing image frames within said sealed cavity, in use. The image sensor comprises a detector region defining an array of pixels, a screen member located, in use, within the cavity between the radioactive source and the detector, said screen member having at least one aperture, and a processor for retrieving said captured image frames, monitoring said image frames for changes in the statistical distribution of active pixels and, in the event that statistical distribution of active pixels indicates the presence of a feature in an image frame, generating a tamper alert.

A tamper resistance wall structure on a circuit board includes a wall body formed of a laminated board, and a tamper detection wiring provided in the wall body. An outer through hole is provided in an outer surface of the wall body, which is a side surface away from a protective area on the circuit board, and is formed perpendicular to a longitudinal direction of the outer surface and perpendicular to the circuit board. An inner through hole is provided in an inner surface of the wall body, which is a side surface close to the protective area on the circuit board, and is formed perpendicular to a longitudinal direction of the inner surface and perpendicular to the circuit board. A recess is formed on the inner surface, and the inner through hole is formed in the recess and is a part of the tamper detection wiring.

The present invention provides a security assembly for protecting a device includes first and second security wraps fitted to the device. The first security wrap covers a first area of the device. The second security wrap partially overlaps the first security wrap and covers a second area of the device. Each of the first and second security wraps has a security screen having first and second screen terminals and a conductive track extending between the first and second screen terminals. A conductive structure is disposed in an overlapping area between the first and second security wraps and coupled to the second screen terminal of the first security screen and to the first screen terminal of the second security screen.

A cap chip or high density reroute layer for use in a stacked microelectronic module. A first set of electrically conductive reroute layers are defined on a sacrificial substrate. One or more stud bump columns are defined on an exposed conducive pad on a conductive reroute layer. One or more active or passive electronic elements, or both may be electrically coupled to one or more exposed conductive pads. The layer is encapsulated in an encapsulant and the stud bump columns exposed by removing a portion of the encapsulant. A second set of electrically conductive reroute layers is defined on the layer and electrically coupled to the stud bumps. The sacrificial substrate is removed to provide a cap chip or reroute layer.

A circuit board is protected by being enclosed in a security housing that includes conductive tamper traces running along its interior surface, the conductive tamper traces being a housing portion of a tamper detection circuit. The tamper detection circuit also includes a board portion that detect tampering with the tamper detection circuit by monitoring voltages at monitor nodes along the board portion. The board portion of the tamper detection circuit is connected to the tamper traces via multiple connector pieces. The connector pieces can be held in place by board connector piece holders affixed to the board or housing connector piece holders of the housing. When tampering is detected, it can be localized based on voltages measured at multiple recesses along the housing. The tamper detection circuit can be arranged in a wheatstone bridge layout for environmental tolerance. The circuit board's functions/components can be disabled if tampering is detected.

In an example, monitoring circuitry includes a first and second coupling, at least one of which is to capacitively couple the monitoring circuitry to a monitored circuit on a product packaging. The monitored circuit has a resistance which is indicative of a status of a product stored in the product packaging, and the monitored circuit is to be connected in series between the first coupling and the second coupling. The monitoring apparatus may determine the resistance of the monitored circuit via the first and second couplings.