Patent classifications
H05K3/0017
Methods for producing an etch resist pattern on a metallic surface
A method of forming a metallic pattern on a substrate is provided. The method includes applying onto a metallic surface, a chemically surface-activating solution having an activating agent that chemically activates the metallic surface; non-impact printing an etch-resist ink on the activated surface to produce an etch resist mask according to a predetermined pattern, wherein at least one ink component within the etch-resist ink undergoes a chemical reaction with the activated metallic surface to immobilize droplets of the etch-resist ink when hitting the activated surface; performing an etching process to remove unmasked metallic portions that are not covered with the etch resist mask; and removing the etch-resist mask.
METHOD OF MANUFACTURING FLEXIBLE SUBSTRATE
According to one embodiment, a method of manufacturing a flexible substrate, includes forming a release layer on a glass substrate, forming an insulating base, forming a plurality of insulating layers, wiring lines and electrical elements, asking the release layer, the insulating base and the plurality of insulating layers from above to the glass substrate via a mask, forming an upper resin layer, removing the glass substrate and the release layer by peeling off an interface between the release layer and the insulating base and forming a lower resin layer so as to be in contact with a lower surface of the insulating base and a lower surface of the upper resin layer.
Wiring circuit board and producing method thereof
A wiring circuit board includes an alignment mark layer. The alignment mark layer includes a first alignment mark and a second alignment mark. The condition A or the condition B is satisfied. Condition A: The first alignment mark has a first portion (a first starting point portion or a first center of gravity portion). The second alignment mark has a second portion (a second starting point portion or a second center of gravity portion). Condition B: The first alignment mark has the first portion, and the second alignment mark does not have the second portion, or the first alignment mark does not have the first portion, and the second alignment mark does not have the second portion.
Sealed package and method of forming same
Various embodiments of a sealed package and a method of forming such package are disclosed. The package can include a non-conductive substrate that includes a cavity disposed in a first major surface. A cover layer can be disposed over the cavity and attached to the first major surface of the non-conductive substrate to form a sealed enclosure. The sealed package can also include a feedthrough that includes a via between a recessed surface of the cavity and a second major surface of the substrate, and a conductive material disposed in the via. An external contact can be disposed over the via on the second major surface of the non-conductive substrate, where the external contact is electrically connected to the conductive material disposed in the via. The sealed package can also include an electronic device disposed within the sealed enclosure that is electrically connected to the external contact.
PRINTED CIRCUIT BOARD AND PACKAGE SUBSTRATE INCLUDING SAME
A printed circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; and a pad disposed on the first insulating layer and exposed through the cavity; wherein the second insulating layer includes a first portion disposed on an upper surface of the first insulating layer in a region where the cavity is formed; and a second portion other than the first portion, and wherein a thickness of the first portion is smaller than a thickness of the second portion.
METHOD FOR MAKING A RECESS OR OPENING INTO A PLANAR WORKPIECE USING SUCCESSIVE ETCHING
A method for making a recess or opening in a planar workpiece with a thickness of less than 3 millimeters includes successively etching a plurality of flaws to form the recess or opening such that a contour of the recess or opening has a sequence of widenings and constrictions as a result of the etching.
Method for making a heat dissipation structure
An electronic device includes a heat dissipation structure. The heat dissipation structure comprises a flexible substrate, a graphite sheet, and a heat insulating material. The flexible substrate comprises a first surface and a second surface facing away from the first surface. The flexible substrate is disposed on the graphite sheet, and the second surface faces the graphite sheet. At least one containing cavity is formed between the flexible substrate and the graphite sheet. The heat insulating material is filled in the containing cavity. A cover plate is disposed on the first surface. At least one groove is formed on the flexible substrate from the first surface to the second surface. The groove is sealed by the cover plate to formed a sealed cavity. A phase changing material is filled in the sealed cavity.
Printed circuit board
A printed circuit board includes: a first insulating layer; a first wiring layer at least partially buried in the first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a second wiring layer at least partially buried in the second insulating layer; and a cavity penetrating through the second insulating layer and a portion of the first insulating layer and exposing a portion of the upper surface of the first insulating layer as a bottom surface of the cavity. The first wiring layer includes a wiring pattern at least partially exposed from the first insulating layer by the cavity, an upper surface of the wiring pattern has a step structure with the upper surface of the first insulating layer exposed by the cavity, and a lower surface of the wiring pattern is coplanar with a lower surface of the first insulating layer.
Method for producing wiring substrate
The present disclosure provides a method for producing a wiring substrate. A seeded substrate including an insulation substrate, a conductive undercoat layer, and a conductive seed layer provided in a first region, in that order, is first prepared. An insulation layer covering the seed layer and the undercoat layer is then formed. Subsequently, the insulation layer is etched to expose a surface of the seed layer and form a remaining insulation layer covering the undercoat layer in the second region. Subsequently, a voltage is applied between an anode and the seed layer while a solid electrolyte membrane containing a metal ion-containing aqueous solution disposed between the seed layer and the anode and the membrane and the seed layer pressed into contact with each other, thereby a metal layer being formed on the surface of the seed layer. Thereafter, the remaining insulation layer is removed and the undercoat layer is etched.
PACKAGING STRUCTURE
A packaging structure, includes: a dielectric layer; at least one inner wiring layer embedded in the dielectric layer; at least two outer wiring layers arranged two sides of the at least one inner wiring layer and combined with the dielectric layer; and at least one electronic component embedded in the dielectric layer; each inner wiring layer including at least two spaced supporting pads, and each supporting pad including a main body and a protruding portion extending outward from a periphery of the main body, the packaging structure further including at least two spaced positioning pillars, and each positioning pillar correspondingly connected to one main body, each electronic component arranged between at least two positioning pillars, and an end of each electronic component being in contact with protruding portions of at least two supporting pads, thereby packaging the electronic component accurately.