A polishing composition is for polishing a resin, and includes alumina abrasive grains, a dispersant, and water. A ratio between a primary average particle size of alumina particles in the alumina abrasive grains and an average particle size of the alumina particles measured by dynamic light scattering is 1:6.0 to 1:100.

Disclosed is a method of manufacturing a wiring board, which allows a desmearing process to be carried out appropriately without roughening a surface of an insulating layer. The method of manufacturing a wiring board includes a light irradiation step for irradiating a wiring board material with ultraviolet light in an atmosphere containing oxygen. The wiring board material has an insulating layer laminated on a conductive layer, a protective layer formed on the insulating layer, and a through hole (viahole) that penetrates the insulating layer and the protective layer. The method also includes a plating step for forming a plating layer, which is made from a conductive material, on the surface of the wiring board material from which the protective layer has been removed. The surface of the wiring board material includes a bottom of the through hole.

Doped, low-temperature co-fired ceramic (LTCC) insulating substrates and related wiring boards and methods of manufacture are disclosed. The doped, LTCC insulating substrate is formed from a baked (e.g., sintered) glass-ceramic aggregate material formed from a glass material, a ceramic filler material, and a composite oxide. The crystallized glass-ceramic aggregate is then doped with Iron and/or Manganese before baking. Iron or Manganese can further reduce dielectric loss and the loss tangent of the LTCC insulating substrate formed from that glass material. The glass material becomes crystallized due to an oxide crystal phase being deposited on the glass material during baking, which reduces the dielectric losses. This may be important for the application use as wiring boards for high radio-frequency (RF) electrical circuits where low dielectric loss and loss tangent is desired to achieve a desired signal transmission delay performance.

Doped, low-temperature co-fired ceramic (LTCC) insulating substrates and related wiring boards and methods of manufacture are disclosed. The doped, LTCC insulating substrate is formed from a baked (e.g., sintered) glass-ceramic aggregate material formed from a glass material, a ceramic filler material, and a composite oxide. The crystallized glass-ceramic aggregate is then doped with Iron and/or Manganese before baking. Iron or Manganese can further reduce dielectric loss and the loss tangent of the LTCC insulating substrate formed from that glass material. The glass material becomes crystallized due to an oxide crystal phase being deposited on the glass material during baking, which reduces the dielectric losses. This may be important for the application use as wiring boards for high radio-frequency (RF) electrical circuits where low dielectric loss and loss tangent is desired to achieve a desired signal transmission delay performance.

A present invention provides a method for manufacturing a printed wiring board having excellent plating adhesion to a resin substrate having low surface roughness such as having surface roughness Ra of 0.2 m or less, having excellent treating solution stability, and having high penetrability into the resin substrate. The method for manufacturing a resin substrate includes a step 1A or a step 1B; and a step 2 after the step 1A or the step 1B; and the steps are conducted before conducting electroless plating.

The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

A printed circuit board for an electric component contains an electrically insulating substrate which has a surface and at least one electrically conductive conductor track formed within the substrate. The surface of the substrate has a sealing region which is arranged and/or configured such that the sealing region is flat and/or the substrate has a homogenous substrate thickness in the sealing region. An overmolding which adjoins the sealing region is arranged on the surface of the substrate.

A fabrication method of a circuit includes drilling holes in a substrate, so as to form a plurality of first opening holes and second opening holes in the substrate. A cover film is attached onto the substrate, so as to cover the first opening holes and the second opening holes. A portion of the cover film covering the first opening holes is removed, so as to expose the first opening holes. The first opening holes are filled.

A multilayer printed wiring board and a method of manufacturing the same are provided. A multilayer printed wiring board of the present embodiment includes: a core base material formed by laminating a first wiring layer and a first insulating layer in this order on an insulating substrate; and a built-up layer formed by laminating a second wiring layer and a second insulating layer in this order on the core base material. A primer layer is formed between the second wiring layer and the first insulating layer, the second wiring layer has a lower surface at least part of which is in contact with the primer layer, and the second wiring layer has an upper surface and a side surface on both of which a tin-plated layer and a silane coupling layer are formed in this order.

The method for manufacturing an insulated circuit board of the present invention includes: a ceramic/aluminum-joining step of joining an aluminum material to a ceramic substrate and thereby, forming an aluminum layer; a titanium material-disposing step of disposing a titanium material on a surface of the aluminum layer or the aluminum material in a circuit pattern shape; a titanium layer-forming step of performing a heat treatment in a state where the titanium material is laminated on the surface of the aluminum layer or the aluminum material and thereby, forming the titanium layer; and an etching treatment step of etching the aluminum layer on which the titanium layer is formed, into the circuit pattern shape.