A printed wiring board includes a lower layer including conductor layers and insulating layers, a conductor layer formed on the outermost insulating layer in the lower layer, and a solder resist layer formed on the conductor layer such that the solder resist layer is covering the conductor layer on the outermost insulating layer, and a two-dimensional code structure formed on the lower layer and including the conductor layer and a portion of the solder resist layer such that the portion of the solder resist layer has openings forming exposed portions of the conductor layer and that the openings of the solder resist layer and the exposed portions of the conductor layer form the two-dimensional code structure. The conductor layer includes a portion corresponding to the two-dimensional code structure such that the portion of the conductor layer has a residual copper rate that allows the two-dimensional code structure to be read.

The invention, which relates to the technical field of inductance embedding, specifically discloses an embedded circuit board. The embedded circuit board includes: at least layer of sub-body, where preset positions of the sub-bodies are provided with through slots; and an inductance element embedded within the slots and configured to be spaced apart from sidewalls of the slots. In the above manner, it is possible to make the embedded circuit board of the present application structurally compact, highly integrated, widely applicable, and safe and reliable.

An exposure device that draws a pattern on a substrate by shining a beam from a light source device on substrate and scanning the beam in a main scanning direction while varying the intensity of beam according to pattern information, including: a scanning unit having a beam scanning unit that includes a polygonal mirror whereby the beam is oriented to scan the beam, and light detector for photoelectric detection of reflected light generated when beam is shined on substrate; an electro-optical element for controlling the beam's intensity modulation according to pattern information such that at least part of second pattern to be newly drawn is drawn on top of at least part of first pattern formed on substrate; and a measurement unit measuring relative positional relationship between the first and second pattern on the basis of a detection signal output by the detector while second pattern is drawn on substrate.

A process for manufacturing an electronic component having attaches includes providing a first component having a first attach, forming trenches on a portion of the first attach with a laser to form a solder stop, and providing a second component comprising a second attach. The process further includes providing solder between the first attach and the second attach to form a connection between the first component and the second component, where the trenches contain the solder to a usable area. A device produced by the process is disclosed as well.

Manufacturing a rigid-flex circuit board includes providing an inner flexible circuit board and a first flexible metal clad laminate, laminating the first flexible metal clad laminate on a surface of the inner flexible circuit board through a first adhesive film, causing the first copper layer to form a third conductive circuit layer, partially covering the metal protective layer exposed by the third conductive circuit layer, removing the metal protective layer exposed by the third conductive circuit layer and the covered area, providing a second copper foil, laminating the second copper foil on a surface of the third conductive circuit layer through a second adhesive film, removing the metal protective layer at the opening area, and causing the second copper foil to form a fifth conductive circuit layer. The first flexible metal clad laminate includes a second base material layer, a metal protective layer, and a first copper layer.

A method for preparing a conductive circuit can begin with the preparation of a non-conductive substrate having a top surface and a bottom surface, and then utilizing a pulse laser to create a top circuit pattern upon the top surface, a bottom circuit pattern upon the bottom surface, and a through hole connecting the top circuit pattern with the bottom circuit pattern. Subsequently, a conductive circuit is formed upon the top circuit pattern and the bottom circuit pattern and inside the through hole, wherein the conductive circuit is restricted from being formed upon the top surface outside of the top isolation region and the bottom surface outside of the bottom isolation region.

Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.

A direct patterning method of touch panel is provided. A substrate having a display region and a peripheral region is provided. A periphery circuit having a bonding pad is disposed on the periphery region. A metal nanowire layer made of metal nanowires are disposed on the display region and the peripheral region. A photosensitive pre-cured layer is disposed on the metal nanowire layer. A photolithography process is performed, which includes exposing the pre-cured layer to define a removal area and a reserved area, and removing the pre-cured layer and the metal nanowire layer on the removal area using a developer solution to form a touch-sensing electrode disposed on the display region and to expose the bonding pad disposed on the periphery region. The touch sensing electrode made of the pre-cured layer and the metal nanowire layer is electrically connected to the periphery circuit.

Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region 308 within the conductive structure. Other embodiments are described and claimed.

Disclosed are a hole connecting layer manufacturing method, a circuit board manufacturing method and a circuit board. The hole connecting layer manufacturing method comprises: adhering a first insulating dielectric layer, used for laminating and filling, to a daughter board; laminating and solidifying the first insulating dielectric layer on the daughter board; adhering a second insulating dielectric layer, used for laminating and filling, to the first insulating dielectric layer which has been laminated and solidified; manufacturing a first receiving hole on the first insulating dielectric layer and a second receiving hole on the second insulating dielectric layer, wherein the first receiving hole and the second receiving hole are provided vertically opposite to each other; filling both the first receiving hole and the second receiving hole with a conductive medium to complete manufacturing of the hole connecting layer.