Patent classifications
H05K3/04
Method and structure for alignment of lens to optical product at PCBA level
An optical package includes: a Printed Circuit Board including a plurality of cut-out sections; a lens, including a first plurality of protrusions corresponding respectively to the plurality of cut-out sections, wherein when the lens is placed under the PCB, the protrusions will pass through the cut-out sections; and a sensor for attaching on to the lens and the PCB. The first plurality of protrusions has a shape from the group including: snap features, guide posts and guide posts with tight-fit ribs.
EMBEDDED HIGH VOLTAGE TRANSFORMER COMPONENTS AND METHODS
Disclosed are apparatus and methods for embedded high voltage transformer components. Industrial applications require transformers that provide high voltage isolation. The laminate materials used for fabricating Printed Circuit Boards (PCB) are very good insulators and PCB transformers can provide higher voltage isolation than traditional wire wound devices. There are a variety of PCB laminate materials with different properties for voltage breakdown. FR-4 laminate is commonly used and has voltage breakdown properties exceeding 10 kV/mm. To produce PCB transformers with breakdown voltages exceeding 5 kV, it is beneficial to use laminate with much higher breakdown voltages. Generally, the materials with high breakdown voltage cost more. High voltage isolation can be achieved at a moderate cost by mixing low cost FR-4 laminate with high voltage dielectric materials.
DRIVING SUBSTRATE, MANUFACTURING PROCESS, AND MICRO-LED ARRAY LIGHT-EMITTING BACKLIGHT MODULE
The present disclosure relates to a driving substrate, a manufacturing method, and a micro-LED array substrate light-emitting backlight module. The driving substrate includes a first metal layer, a first high-reflection layer, and a second metal layer stacked in a top-down sequence. The driving substrate, the manufacturing method, and the micro-LED array light emitting backlight module of the present disclosure solve the loss of reflectivity issue caused by the edge forbidden area of the electrode welding pad edge forbidden region. At the same time, the limited reflectivity of traditional coated high-reflective layers (such as white oil) may also be enhanced.
DRIVING SUBSTRATE, MANUFACTURING PROCESS, AND MICRO-LED ARRAY LIGHT-EMITTING BACKLIGHT MODULE
The present disclosure relates to a driving substrate, a manufacturing method, and a micro-LED array substrate light-emitting backlight module. The driving substrate includes a first metal layer, a first high-reflection layer, and a second metal layer stacked in a top-down sequence. The driving substrate, the manufacturing method, and the micro-LED array light emitting backlight module of the present disclosure solve the loss of reflectivity issue caused by the edge forbidden area of the electrode welding pad edge forbidden region. At the same time, the limited reflectivity of traditional coated high-reflective layers (such as white oil) may also be enhanced.
Method of forming patterned metal unit, and patterned article formed with the same
A method of forming a patterned metal unit on an article. The method includes the steps of: providing an article that has an insulating surface; transferring a catalyst layer onto the insulating surface of the article, the catalyst layer including a catalytic material; removing a part of the catalyst layer to form a patterned catalyst layer; and forming a patterned metal layer on the patterned catalyst layer by an electroless plating technique to obtain a patterned metal unit that is constituted by the patterned catalyst layer and the patterned metal layer.
Package substrate
A package substrate includes a dielectric layer, a first circuit layer, a second circuit layer and at least one electrically conductive pole. The dielectric layer includes a first side and a second side opposite to the first side. The first circuit layer is located at the first side of the dielectric layer, and includes a plurality of spaced first circuit patterns embedded into the dielectric layer. The second circuit layer is located at the second side of the dielectric layer, and includes a plurality of spaced second circuit patterns located on the second side the dielectric layer. The electrically conductive pole electrically couples the first circuit layer to the second circuit layer. Each of the first circuit patterns has an extension direction from the first side toward the second side, and has widths gradually decreasing along the extension direction.
SNAP-RF INTERCONNECTIONS
A radio frequency connector includes a substrate, a first ground plane disposed upon the substrate, a signal conductor having a first contact point, with the first contact point being configured to electrically mate with a second contact point, and a first ground boundary configured to electrically mate with a second ground boundary, with the first ground boundary being formed as an electrically continuous conductor within the substrate.
SNAP-RF INTERCONNECTIONS
A radio frequency connector includes a substrate, a first ground plane disposed upon the substrate, a signal conductor having a first contact point, with the first contact point being configured to electrically mate with a second contact point, and a first ground boundary configured to electrically mate with a second ground boundary, with the first ground boundary being formed as an electrically continuous conductor within the substrate.
COPPER FOIL WITH CARRIER, CORELESS SUPPORT WITH WIRING LAYER, AND METHOD FOR PRODUCING PRINTED CIRCUIT BOARD
There is provided a copper foil provided with a carrier exhibiting a high peeling resistance against the developer in the photoresist developing process and achieving high stability of mechanical peel strength of the carrier. The copper foil provided with a carrier comprises a carrier; an interlayer disposed on the carrier, the interlayer having a first surface adjacent to the carrier and containing 1.0 atom % or more of at least one metal selected from the group consisting of Ti, Cr, Mo, Mn, W and Ni and a second surface remote from the carrier and containing 30 atom % or more of Cu; a release layer disposed on the interlayer; and an extremely-thin copper layer disposed on the release layer.
Redistribution plate
A single-layer redistribution plate functioning as a space translator between a device under testing (DUT) and a testing PCB may comprise a hard ceramic plate. A DUT side of the plate may have pads configured to interface with a device under testing. Both sides of the plate may comprise traces, vias, and pads to fan out the DUT pad pattern so that the plate side opposite the DUT side has spatially translated pads configured to interface with the pads on a testing PCB. Fabricating a redistribution plate may comprise calibrating and aligning, laser milling vias, laser milling trenches and pads, copper plating, grinding and polishing, removing residual copper, and coating the copper surfaces.