Printed circuit boards may be formed using ceramic substrates with high thermal conductivity to facilitate heat dissipation. Metal nanoparticles, such as copper nanoparticles, may be used to form conductive traces and fill through-plane vias upon the ceramic substrates. Multi-layer printed circuit boards may comprise two or more ceramic substrates adhered together, wherein each ceramic substrate has one or more conductive traces defined thereon and the one or more conductive traces are formed through consolidation of metal nanoparticles. The one or more conductive traces in a first ceramic substrate layer are in electrical communication with at least one second ceramic substrate layer adjacent thereto.

A flexible circuit (FC) and a method of forming the FC each include providing a first dielectric layer, applying a plurality of conductive circuit traces that are substantially parallel to each other to the first dielectric layer, providing a second dielectric layer atop the first dielectric layer and the plurality of conductive circuit traces to form a third dielectric layer having the plurality of conductive traces disposed therein and being configured to support and insulate the plurality of conductive traces, and forming a plurality of channels extending at least partially through a thickness of the third dielectric layer, wherein the plurality of channels are arranged between the plurality of conductive circuit traces and substantially parallel thereto and are configured to provide increased flexibility of the FC.

The present description relates to a method of manufacturing an electronic circuit (30) comprising: a support (32), an assembly site (31) having a first surface protruding from said support intended to be assembled to an assembly site of another electronic circuit by a self-assembly method; and a peripheral area (39) around said assembly site, the assembly site (31) comprising at least one level, each level comprising conductive pads (34) and insulating posts (380) between the conductive pads, said manufacturing method comprising the forming of said at least one level of the assembly site, such that the edges, in at least one direction (X) of the main plane (XY), of each level of the assembly site and the locations, in the at least one direction (X), of the conductive pads and of the insulating posts of the same level are defined in a same photolithography step of said method.

A circuit board includes at least two circuit board units stacked together. Each circuit board unit includes a substrate and a circuit layer. The substrate defines a conductive hole penetrating therethrough. The conductive hole provided with a conductor therein. One side of the substrate further defines a groove, the groove including a concave portion aligned with the conductive hole. The circuit layer includes a connection pad located in the concave portion. The connection pad is shaped as a conductive protrusion, which surrounds and is electrically connected to the conductor. The circuit layer is located in the groove, and the conductive hole is electrically connecting the circuit layers of the circuit board units.

A method for manufacturing a wiring substrate includes forming a second resin insulating layer on a first resin insulating layer such that the second resin insulating layer is in contact with a surface of the first resin insulating layer, irradiating laser upon the second resin insulating layer such that a recess penetrating through the second resin insulating layer and exposing the first resin insulating layer is formed, and forming a conductor layer including conductor material filled in the recess formed through the second resin insulating layer such that the conductor layer is embedded in the second resin insulating layer. The second resin insulating layer are formed on the surface of the first resin insulating layer such that the first resin insulating layer and the second resin insulating layer have different processability with respect to the laser.

A method for producing a structure, comprising providing a Composite Conductive Substrate (CCS) with a conductive layer, a non-conductive layer and a release layer, implemented on top of the conductive layer; determining an empty conductive pattern for each layer of the structure; printing a layer of non-conductive matter on the CCS, such that the conductive pattern of the first layer left empty from the non-conductive matter; on top of the release layer, below which the conductive layer is implemented, filling the empty conductive pattern with conductive matter by electroplating; peeling the filled conductive matter or peeling the filled conductive matter and the printed non-conductive matter, from the conductive layer of the CCS.

A wiring substrate includes a first insulating layer, a conductor layer including first and second conductor pads, a second insulating layer having an opening exposing the second conductor pads, and a wiring structure including a resin insulating layer and a wiring layer and formed in the opening of the second insulating layer. The wiring structure has first surface side connection pads, second surface side connection pads and electrically connected to the second conductor pads of the conductor layer, and conductors that electrically connect the first surface side connection pads and the second surface side connection pads, the first surface side connection pads form a component mounting surface having first and second component mounting region, and the first surface side connection pads include a group of pads in the first region and a group of pads in the second region electrically connected to the group of pads in the first region.

Pastes are disclosed that are configured to coat a passage of a substrate. When the paste is sintered, the paste becomes electrically conductive so as to transmit electrical signals from a first end of the passage to a second end of the passage that is opposite the first end of the passage. The metallized paste contains a lead-free glass frit, and has a coefficient of thermal expansion sufficiently matched to the substrate so as to avoid cracking of the sintered paste, the substrate, or both, during sintering.

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a core with a first surface and a second surface, where the core comprises glass. In an embodiment, a first buildup layer is over the first surface of the core, and a second buildup layer is under the second surface of the core. In an embodiment, the electronic package further comprises a via through the core between the first surface of the core and the second surface of the core, and a plane into the first surface of the core, where a width of the plane is greater than a width of the via.

In one aspect, a PCB is provided. The PCB includes at least one insulating layer, a blind slot, and at least one via. The at least on insulating layer includes a first surface and a second surface opposite the first surface. The blind slot is plated and formed in the at least one insulating layer, where the blind slot partially extends from the first surface to the second surface, and where the blind slot includes a conductive plating bonded along a major surface of the blind slot. The at least one via is electrically conductive and filled, where the at least one via is coupled with and extends between the conductive plating of the blind slot and the second surface of the at least one insulating layer.