A process for making a circuit board modifies a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. The catalytic laminate is subjected to a drilling and resin-rich surface removal operation to expose the catalytic particles, followed by an electroless plating operation which deposits a thin layer of conductive material on the surface. A photo-masking step follows to define circuit traces, after which an electro-plating deposition occurs, followed by a resist strip operation and a quick etch to remove electroless copper which was previously covered by photoresist.

A printed wiring board according to an aspect of the present invention includes a base film having insulation properties and a conductive pattern including multiple wiring portions laminated, the conductive pattern running on at least one surface of the base film, wherein each wiring portion includes a first conductive portion and a second conductive portion coating an outer surface of the first conductive portion, wherein an average width of each wiring portion is 10 μm or greater to 50 μm or smaller, and an average thickness of the second conductive portion is 1 μn or greater to smaller than 8.5 μm.

The present invention is directed to provide novel composite copper components. For example, provided is a composite copper component including a copper oxide-containing layer formed on at least a portion of the surface of a copper component, in which when the surface of the composite copper component is bonded to a resin substrate by thermocompression, and the copper component is peeled off from the resin substrate after the thermocompression bonding, metal contained in the copper oxide-containing layer is transferred to the resin substrate.

A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

Disclosed is a method for manufacturing a wiring structure including a step of forming a wiring on an insulating resin layer. The step of forming the wiring includes: forming a modified region including pores in a surface layer of the insulating resin layer by treating a surface of the insulating resin layer with a treatment method including surface modification; forming a seed layer on the surface of the insulating resin layer by sputtering; and forming the wiring on the seed layer by electrolytic copper plating. The disclosed method may include, in this order: a step of forming a surface treatment agent layer that covers a surface of the wiring by treating the surface of the wiring with a surface treatment agent for improving adhesion; and a step of forming a modified region including pores in a surface layer of a first layer of the insulating resin layer by treating the surface of the first layer of the insulating resin layer with a treatment method including surface modification.

A method of manufacturing a printed circuit board includes forming an intermediate layer on a first conductive layer disposed on a first insulating layer, forming a second conductive layer and a second insulating layer on the intermediate layer, separating the first insulating layer from at least one portion of the first conductive layer, and etching the first conductive layer and the intermediate layer. After the etching, a surface of the second conductive layer protrudes further than a surface of the second insulating layer. The intermediate layer before the etching includes a portion overlapping the second conductive layer in a vertical direction and another portion not overlapping the second conductive layer in the vertical direction.

A printed wiring board includes a first insulating layer, a first conductor layer formed on first surface of the first insulating layer, a second conductor layer formed on second surface of the first insulating layer, a first via structure formed in the first insulating layer such that the first via structure is connecting the first and second conductor layers, a second insulating layer formed on the second surface of the first insulating layer such that the second conductor layer is embedded into the second insulating layer, a third conductor layer formed on the second insulating layer, and a second via structure formed in the second insulating layer such that the second via structure is connecting the second and third conductor layers. The second conductor layer includes a dedicated wiring layer which transmits data between two electronic components to be mounted to the first surface of the first insulating layer.

A printed circuit board includes: a first insulating layer; a circuit pattern protruding from an upper surface of the first insulating layer and having recesses in side surfaces thereof; and a metal portion covering an upper surface and each of both side surfaces of the circuit pattern. The first insulating layer is spaced apart from at least a portion of a lower surface of the circuit pattern.

In a method for producing a wired circuit board includes a step (1), in which the insulating layer having an inclination face is provided; a step (2), in which a metal thin film is provided on the surface of the insulating layer including the inclination face; a step (3), in which a photoresist is provided on the surface of the metal thin film; a step (4), in which a photomask is disposed so that a first light exposure portion and a second light exposure portion in the photoresist are exposed to light, and the photoresist is exposed to light; a step (5), in which the first light exposure portion and the second light exposure portion are removed; and a step (6), in which the first wire and the second wire are provided on the surface of the metal thin film.

The invention pertains to a method for the bonding of a component embedded into a printed circuit board exhibiting the following steps: Provision of a core exhibiting at least one insulating layer and at least one conductor layer applied to the insulating layer, Embedding of at least one component into a recess of the insulating layer, wherein the contacts of the component are essentially situated in the plane of an outer surface of the core exhibiting the at least one conductor layer, Application of a photoimageable resist onto the one outer surface of the core on which the component is arranged, while filling the spaces between the contacts of the component, Clearing of end faces of the contacts and of the areas of the conductor layer covered by the photoimageable resist by exposing and developing the photoimageable resist, by application of a semi-additive process, deposition of a layer of conductor material onto the cleared end faces of the contacts and the cleared areas of the conductor layer and formation of a conductor pattern on at least the one outer surface of the core on which the component is arranged, as well as the interconnecting paths between the contacts and the conductor pattern, and Removal of the areas of the conductor layer not belonging to the conductor pattern.