An apparatus and method to permit reconfiguration of a memory topology. A printed circuit board (PCB) has a central processing unit (CPU) connector coupled a pair of dual inline memory module (DIMM) connectors coupled thereto. The PCB defines an electrical access channel coupling the pair of DIMM connectors into a T topology having a first branch and a second branch. The second branch of the T topology is electrically discontinuous with the rest of the T topology proximate to a T junction. A bridge may be provided to span the discontinuity.

A battery pack including a battery cell having an electrode assembly of a cathode/separator/anode structure mounted in a battery case together with an electrolyte in a sealed state, and a protection circuit module (PCM) electrically connected to the battery cell. The PCM includes a protection circuit board (PCB) electrically connected to the battery cell, the PCB being provided on a region where a circuit is connected with a conductive pattern including a fusing part, having relatively high resistance, configured to fuse itself for interrupting the flow of current when a large amount of current is conducted.

In accordance with an embodiment, a method for manufacturing an electric circuit that includes providing a support having a first region, the first region having a first conductor that has a first sidewall and a second conductor that has a second sidewall, wherein the first conductor is electrically isolated from the second conductor is provided. A distance between the first sidewall and the second sidewall is increased using a technique such as stamping, etching, or trimming. A first circuit element is coupled to the first conductor and encapsulated in a mold compound. In accordance with another embodiment, an electric circuit includes a support having interconnect with sidewalls wherein notches extend from one or more of the sidewalls into the interconnect. A circuit element is coupled to the interconnect by a bonding agent and protected by a protective structure.

A circuit may include a first transmission line that includes a first first-line conductor configured to transport a signal and a second first-line conductor. The circuit may also include a second transmission line that includes a first second-line conductor, a second second-line conductor electrically coupled to the second first-line conductor, and a third second-line conductor separated from and positioned between the first and second second-line conductors. The third second-line conductor may be electrically coupled to the first first-line conductor. The circuit may also include a conductive jumper electrically coupling the first and second second-line conductors. The conductive jumper may contact the first and second second-line conductors in a position near the coupling of the first and second transmission lines.

An apparatus and method to permit reconfiguration of a memory topology. A printed circuit board (PCB) has a central processing unit (CPU) connector coupled a pair of dual inline memory module (DIMM) connectors coupled thereto. The PCB defines an electrical access channel coupling the pair of DIMM connectors into a T topology having a first branch and a second branch. The second branch of the T topology is electrically discontinuous with the rest of the T topology proximate to a T junction. A bridge may be provided to span the discontinuity.

A method for transmitting data advantageously reduces cross-talk in high-speed data transmission. The method comprises receiving an input data word, encoding the input data word into a code word, and driving the code word on to an interconnect for transmission. The code word is generating using a balanced coding scheme, and the interconnect is a single-ended, twisted-wire on-chip fly-over interconnect. A receiver circuit decodes the code word to generate an output data word.

A printed circuit board is disclosed. The printed circuit board comprises a substrate having a top surface and a bottom surface. A ground plane is on the bottom surface. A signal trace is on the top surface along a first direction. At least two isolated power planes are on the top surface adjacent to opposite sides of the signal trace, respectively. A conductive connection along a second direction couples to the two power planes, across the signal trace without electrically connecting to the signal trace, wherein the signal trace doesn't directly pass over any split of the ground plane.

A circuit arrangement has a populated circuit carrier and includes a flat insulation carrier having a top side and a patterned metallization layer on the top side and a first power semiconductor chip arranged on a first section of the metallization layer. The first power semiconductor chip has a first lower chip load terminal electrically conductively connected to the first section. A shunt resistor is arranged on a second section of the metallization layer. The shunt resistor has a lower main terminal electrically conductively connected to the second section. An electrically conductive connection is provided between the first section and the second section. The electrically conductive connection includes a constriction between the first section and the second section so that a current which flows between the first lower chip load terminal and the lower main terminal during operation of the circuit arrangement must pass through the constriction.

A cable bypass assembly is disclosed for use in providing a high speed transmission line for connecting a board mounted connector of an electronic device to a chip on the device board. The bypass cable assembly has a structure that permits it, where it is terminated to the board mounted connector and the chip member, or closely proximate thereto, to allow signals to be transmitted at greater than 10 GHz with substantially lower loss than a traditional FR4 circuit board.

A chip-on-glass device comprises a chip-on-glass substrate, a metal layer, and a plurality of chip-on-glass connection bumps. The metal layer comprises a plurality of passive jumper routing traces. The plurality of chip-on-glass connection humps is coupled with passive jumper routing traces of the plurality of passive jumper routing traces.