In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.

Methods and systems for verifying compatibility of components of an electronic system are disclosed. The method includes irradiating a first and second components presumably associated with the electronic system, with XRF exciting radiation, and in response thereto, detecting one or more XRF response signals indicative of first and second XRF signatures, emitted from the first and second components. Then the first and second XRF signatures are processed to determine whether they are associated with respectively a first and second XRF marking compositions on the first and second components, and the compatibility of the first and second components to the electronic system is determined/verified based on the correspondence between the first and a second XRF signatures. Electronic systems are also disclosed including at least a first and a second electronic components respectively having the first and second XRF marking compositions that enable verification of compatibility of the components.

A method of producing a conductive path on a substrate including depositing on the substrate a layer of material having a thickness in the range of 0.1 to 5 microns, including metal particles having a diameter in the range of 10 to 100 nanometers, employing a patterning laser beam to selectably sinter regions of the layer of material, thereby causing the metal particles to together define a conductor at sintered regions and employing an ablating laser beam, below a threshold at which the sintered regions would be ablated, to ablate portions of the layer of material other than at the sintered regions.

An organic substrate includes a core layer including organic materials; a first buildup layer on a top surface of the core layer; a second buildup layer on a bottom surface of the core layer; and at least one correction layer formed on at least one part of surfaces of the first buildup layer and the second buildup layer, wherein the correction layer has a thickness which has been calculated using properties of constituent materials including the coefficient of thermal expansion (CTE) and the Young's modulus of the core layer, and CTEs and the Young's modulus of the first and the second buildup layers for reducing warpage of the organic substrate.

The present disclosure relates to a multilayer ceramic substrate preparation method. The multilayer ceramic substrate preparation method according to the present disclosure includes firing a plurality of ceramic green sheets, to create a plurality of ceramic thin films; forming a via hall in each of the plurality of ceramic thin films; filling the via hall of the plurality of ceramic thin films with conductive paste, and heat treating the via hall filled with the conductive paste, to form a via electrode; printing a pattern on a cross section of each of the plurality of ceramic thin films, and heat treating the printed pattern, to form an inner electrode; applying a bonding agent on the cross section of each of the ceramic thin films excluding an uppermost ceramic thin film of the plurality of ceramic thin films; aligning and laminating each of the plurality of ceramic thin films such that each of the plurality of ceramic thin films is electrically connected through the via electrode and the inner electrode; and firing or heat treating the laminated plurality of ceramic thin films.

A processor receives solder paste information, where the solder paste information describes a solder paste used in assembly of a printed circuit board. A processor determines a minimum magnetic force required for removing the solder paste from the printed circuit board based on the solder paste information. A processor receives electromagnet information, where the electromagnet information describes an electromagnet used in cleaning of a misprint of the solder paste on the printed circuit board. A processor determines a minimum amount of power to provide the electromagnet to induce the minimum magnetic force in the electromagnet, where the determination of the amount of power is based on the electromagnet information and the minimum magnetic force. A processor adjusts an amount of power applied to the electromagnet to at least the determined minimum amount of power to clean the misprint of the solder paste from the printed circuit board.

A FPC flattening jig and a FPC flattening method. The FPC flattening jig includes a pressurization mechanism and a heating mechanism; a bottom of the pressurization mechanism has a planar base surface which is used to contact a warped FPC to exert pressure thereon; the heating mechanism is used to heat the pressurization mechanism, such that the planar base surface of the pressurization mechanism has a predefined temperature when exerting pressure on the FPC. The FPC flattening jig heats the pressurization mechanism by a heating mechanism, and then the heated planar base surface of the pressurization mechanism contacts the warped FPC and exerts pressure thereon. Therefore, the FPC can be flattened. As such, the FPC can be reused, facilitating the improvement on the recycling rate of FPC.

A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.

Rework system for unsoldering and/or soldering electronic components on a circuit board, having a work table for fastening the circuit board, having a module which can travel along at least one X-axis and one Y-axis having at least one camera for accommodating electronic components provided on the circuit board, having a drive unit on which the module can travel with the camera, having a control unit for activating the drive unit, having a computing unit to which a display and user-operable input means are assigned, wherein the input means comprises a pointer which can be moved on the display and a command generator which can be operated in a positioning mode for positioning the camera in two steps (rough positioning and fine positioning).

Methods and structures are provided for implementing embedded wire repair for printed circuit board (PCB) constructs. A repair wire layer is provided within the PCB stack with reference planes on opposite sides of the repair wire layer. When a repair connection is required, an appropriate plated through hole (PTH) is drilled to form the repair connection using the repair wire layer.