There is provided an electric connection member having a substrate, an insulating adhesive layer provided on the substrate, and a conductive interconnect, wherein the electric connection member is provided with a recess that opens at a side of the insulating adhesive layer, the conductive interconnect is disposed in the recess, a metal nano-ink is disposed on the conductive interconnect, and all of the metal nano-ink is contained inside the recess.

A seeded substrate is first prepared. The seeded substrate includes an insulation substrate having a main surface composed of a first region and a second region other than the first region, and a conductive seed layer provided on the first region. Subsequently, a conductive layer is formed on at least the second region to obtain a first treated substrate. An insulation layer is then formed on the first treated substrate. The seed layer is then exposed. A metal layer is then formed on the surface of the seed layer. Here, a voltage is applied between the anode and the seed layer while a solid electrolyte membrane containing a metal ion-containing solution being disposed between the second treated substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the insulation layer and the conductive layer are removed.

A substrate for a printed circuit board according to an embodiment of the present invention includes a base film and a metal layer disposed on at least one of surfaces of the base film. In the substrate for a printed circuit board, an amount of nitrogen present per unit area, the amount being determined on the basis of a peak area of a N1s spectrum in XPS analysis of a surface of the base film exposed after removal of the metal layer by etching with an acidic solution, is 1 atomic % or more and 10 atomic % or less.

There is provided a method for manufacturing a printed wiring board that effectively suppresses pattern failure and is also excellent in fine circuit forming properties. This method includes: providing an insulating substrate including a roughened surface; performing electroless plating on the roughened surface of the insulating substrate to form an electroless plating layer less than 1.0 μm thick having a surface having an arithmetic mean waviness Wa of 0.10 μm or more and 0.25 μm or less and a valley portion void volume Vvv of 0.010 μm.sup.3/μm.sup.2 or more and 0.028 μm.sup.3/μm.sup.2 or less; laminating a photoresist on the surface of the electroless plating layer; performing exposure and development to form a resist pattern; applying electroplating to the electroless plating layer; stripping the resist pattern; and etching away an unnecessary portion of the electroless plating layer to form a wiring pattern.

[Object]

To provide a copper clad laminate that is capable of achieving a good volume resistivity at an electroless copper plating layer of a low dielectric resin film while suppressing a transmission loss when being applied to a flexible circuit board, and a method for producing the copper clad laminate.

[Solving Means]

A copper clad laminate of the present invention includes a low dielectric resin film having a relative permittivity of 3.5 or lower and a dissipation factor of 0.008 or lower at a frequency of 10 GHz, and an electroless copper plating layer laminated on at least one surface of the low dielectric resin film. An Ni content in the electroless copper plating layer is 0.01 to 1.2 wt %, and the electroless copper plating layer has a volume resistivity of 6.0 μΩ.Math.cm or lower.

A resin multilayer substrate includes a stacked body provided by stacking and thermocompression bonding resin layers, a first conductor pattern inside the stacked body, and a first protective coating covering at least a first surface and a side surface of the first conductor pattern. The resin layers are made of a first thermoplastic resin, and the first protective coating is made of a second thermoplastic resin. Both of the first and second thermoplastic resins soften at a predetermined press temperature or less. The second thermoplastic resin has a storage modulus lower than a storage modulus of the first thermoplastic resin at a temperature equal to or less than the predetermined press temperature and equal to or more than room temperature.

A wiring substrate includes an insulating layer including inorganic fillers and resin, and a conductor layer formed on a surface of the insulating layer and having a conductor pattern. The surface of the insulating layer has an arithmetic average roughness Ra in the range of 0.05 μm to 0.5 μm, the conductor layer includes a metal film formed on the surface of the insulating layer, and the inorganic fillers include a first inorganic filler including particles such that each of the particles has a portion of a surface separated from the resin and forming a gap with respect to the resin of the insulating layer and that the metal film of the conductor layer includes part formed in the gap between the first inorganic filler and the resin.

A stacking structure is applicable to manufacturing a circuit board. The stacking structure includes a transferring layer and a dielectric layer disposed on the transferring layer. The transferring layer includes a substrate and a thin film disposed on the substrate and having a plurality of recess structures thereon. The recess structures are connected as a single piece and bottom portions and top portions of the recess structures are configured to arrange in a staggered manner to form a multi-dimensional arrangement. At least a portion of the dielectric layer being is located in the recess structures, such that the dielectric layer is at least embedded with the recess structures.

Electronic modules having complex contact structures may be formed by encapsulating panels containing pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within the panel along the cut lines. Holes defining contact regions along the electronic module sidewall may be cut into the panel along the cut lines to expose the buried interconnects. The panel may be metallized, e.g. by a series or processes including plating, on selected surfaces including in the holes to form the contacts and other metal structures followed by cutting the panel along the cut lines to singulate the individual electronic models. The contacts may be located in a conductive grove providing a castellated module.

A conductive network fabrication process is provided and includes filling a hole formed in a substrate with dielectric material, laminating films of the dielectric material on either side of the substrate, opening a through-hole through the dielectric material at the hole, depositing a conformal coating of dielectric material onto an interior surface of the through-hole and executing seed layer metallization onto the conformal coating in the through-hole to form a seed layer extending continuously along an entire length of the through-hole.