A ceramic electronic component of the present disclosure includes a component body including a ceramic layer, at least one terminal electrode provided on one main surface of the component body, and an insulating covering layer provided across the ceramic layer and the terminal electrode to cover part, instead of an entire circumference, of a peripheral edge portion of the terminal electrode, wherein when viewed in plan view from one main surface of the component body, the covering layer intersects with the terminal electrode at a non-perpendicular angle at an intersection of the covering layer and the terminal electrode not covered with the covering layer.

A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side

A three-dimensional circuit board, including a ceramic substrate and multiple circuits, is provided. The ceramic substrate has a first plane, a second plane, a third plane located between the first plane and the second plane, a first side surface connecting the first plane and the second plane, and a second side surface connecting the first plane and the third plane and opposite to the first side surface. A first height of the first side surface is greater than a second height of the second side surface. The circuits are separately embedded on the first plane of the ceramic substrate and extend along the first side surface to be embedded on the second plane.

A manufacturing method of a carrier structure includes: A build-up circuit layer is formed on a carrier. The build-up circuit layer includes at least one first circuit layer, at least one first dielectric layer, a second circuit layer, a second dielectric layer, and a plurality of conductive vias. The first circuit layer is located on the carrier and includes at least one first pad, which is disposed relative to at least one through hole of the carrier. The first dielectric layer is located on the first circuit layer. The second circuit layer is located on the first dielectric layer and includes at least one second pad. The second dielectric layer is located on the second circuit layer and includes at least one opening exposing the second pad. The conductive via penetrates the first dielectric layer and is electrically connected to the first circuit layer and the second circuit layer.

A conductive bump electrode structure includes a substrate, an elastic circuit layer, at least two conductive bumps, and an insulating layer. The elastic circuit layer is mounted on the substrate, and includes at least one elastic circuit. The at least two conductive bumps are mounted on the elastic circuit layer, and are electrically connected to each other through the at least one elastic circuit. The insulating layer is mounted on the elastic circuit layer, and includes at least two holes. Since there is a gap between the conductive bumps, the conductive bump electrode structure is easy to be bent and fit body curves of various parts of a user. The elastic circuit can stretch or compress along with the user's movement due to its elasticity, thereby increasing suitability of the conductive bump electrode structure to the human body.

An interconnect structure includes a first conductor, a second conductor, a dielectric block, a substrate, and a pair of conductive lines. The first conductor and the second conductor form a differential pair design. The dielectric block surrounds the first conductor and the second conductor. The first conductor is separated from the second conductor by the dielectric block. The substrate surrounds the dielectric block and is spaced apart from the first conductor and the second conductor. The pair of conductive lines is connected to the first conductor and the second conductor, respectively, and extends along a top surface of the dielectric block and a top surface of the substrate.

In various embodiments, a chip card module is provided. The chip card module includes a chip card module contact array having six contact pads that are arranged in two rows having three contact pads each in accordance with ISO 7816, and three additional contact pads that are arranged between the two rows. Each additional contact pad is electrically conductively connected to a respective associated contact pad from a row from the two rows.

A printed circuit board includes: a first insulating layer; a circuit pattern protruding from an upper surface of the first insulating layer and having recesses in side surfaces thereof; and a metal portion covering an upper surface and each of both side surfaces of the circuit pattern. The first insulating layer is spaced apart from at least a portion of a lower surface of the circuit pattern.

A printed substrate includes a land that is to be soldered. The land includes a plating film that defines a surface of the land. The plating film includes a metal as a main constituent and a pi-acceptor molecule that is dispersed in the plating film. The pi-acceptor molecule has pi-acceptability and causes ligand field splitting equal to or greater than that of 2,2′-bipyridyl in spectrochemical series. A content of the pi-acceptor molecule in the plating film is equal to or greater than 0.1 weight percent, in terms of carbon atoms, with respect to the metal of the plating film.