A method for manufacturing a circuit board, includes obtaining a second laminated body by laminating, in this order, an uncured second insulating substrate and a resin film on a second surface opposite to a first surface of a cured first insulating substrate of a first laminated body, and performing thermocompression bonding thereon. The first laminated body includes the first insulating substrate and a metal layer that is formed into a pattern shape on the first surface of the first insulating substrate. A third laminated body is obtained by forming a hole that reaches the metal layer, in the resin film, the second insulating substrate, and the first insulating substrate, from a resin film side of the second laminated body, filling conductive paste into the hole, and then peeling off the resin film. Thermocompression bonding is performed by stacking one third laminated body and another third laminated body.

A method of making a printed circuit board structure including a closed cavity is provided. The method can include the steps of forming a cavity in a core structure of a core layer, laminating each of a top surface and a bottom surface of the core structure with an adhesive layer and a metal layer to prepare a laminate structure and cover the cavity to define a closed cavity. The method also includes forming vias through the laminate structure, and patterning the metal layers in the laminate structure.

Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.

A circuit carrier includes a substrate, a first build-up circuit structure, a second build-up circuit structure, a fine redistribution structure and at least one conductive through hole. The substrate has a top surface and a bottom surface opposite to each other. The first build-up circuit structure is disposed on the top surface of the substrate and electrically connected to the substrate. The second build-up circuit structure is disposed on the bottom surface of the substrate and electrically connected to the substrate. The fine redistribution structure is directly attached on the first build-up circuit structure, wherein a line width and a line spacing of the fine redistribution structure are smaller than those of the first build-up circuit structure. The conductive through hole penetrates the fine redistribution structure and a portion of the first build-up circuit structure and is electrically connected to the fine redistribution structure and the first build-up circuit structure.

In one embodiment, an X-ray inspection system may nondestructively inspect a printed circuit board to measure a number of dimensions at a number of pre-determined locations of the printed circuit board. The X-ray inspection system may generate a data set for the printed circuit board based on the measured dimensions. The X-ray inspection system may calculate one or more drilling values based on the data set of the printed circuit board. The X-ray inspection system may provide, to a drilling machine, instructions for drilling a number of plated-through vias based on the calculated drilling values for the printed circuit board.

Research on practical realization of various types of printable devices has progressed, and the realization of devices in which these printable devices are integrated on a flexible board is expected. However, there is the problem that, if a plurality of printable devices are simply integrated on the same board, the area of the integrated device increases, and the yield ratio greatly decreases. An integration technique that solves the problem of an increase in the area and a decrease in the yield ratio is in demand. Electronic devices to be integrated are formed on individual boards, the boards are laid to overlap each other in a predetermined relationship, and then through-vias are formed at predetermined positions. With this, the electronic devices are electrically connected to each other, and function as an integrated device.

According to the present disclosure, a support structure for lighting devices, e.g. LED lighting devices, is provided with an electrically insulating core layer having a first and a second mutually opposed surfaces, with mounting locations for electrically-powered light radiation sources on the first surface, a network of electrically conductive lines printed on said first surface, at least some of said electrically conductive lines extending between the mounting locations and fixed locations on the first surface, and electrical distribution lines of electrically conductive material on the second surface of the core layer, and electrically conductive vias extending through core layer and electrically coupling the electrical distribution lines on the second surface with the electrically conductive lines at said fixed locations on the first surface.

This anisotropic conductive sheet includes: an insulating layer having a first surface and a second surface; and a plurality of conductive paths which are disposed so as to extend in the thickness direction inside the insulating layer and which are respectively exposed to the outside of the first surface and the second surface. The circumferential surface of the conductive paths includes a region where the surface area ratio represented by equation (1) is at least 1.04. Equation (1): surface area ratio = surface area / area

A package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.

Provided are a battery apparatus including: a battery pack including a plurality of battery cells; a battery management system (BMS) for managing the plurality of battery cells; a board to which the BMS is mounted, the board including an insulation layer and a conductive layer; a plurality of wires extending from the plurality of battery cells onto the board; a plurality of through-holes formed in the board, the plurality of wires extending through the plurality of through-holes; a plurality of non-conductive areas, each of the plurality of non-conductive areas being formed on an area around a respective one of the plurality of through-holes; and a plurality of soldering parts, each of the plurality of soldering parts being formed on the respective one of the plurality of through-holes.