Patent classifications
H05K3/4602
Printed wiring board having thermoelectric emlement accommodatred therein
A printed wiring board includes a core substrate including core material and having opening such that the opening penetrates through the core substrate, thermoelectric elements including P-type and N-type thermoelectric elements such that the thermoelectric elements are accommodated in the opening of the core substrate, a first build-up layer that mounts a heat-absorbing element thereon and includes a first resin insulating layer such that the first resin insulating layer is formed on first surface of the core substrate and covering the opening of the core substrate, and a second build-up layer that mounts a heat-generating element thereon and includes a second resin insulating layer such that the formed on the second resin insulating layer is foamed on second surface of the core substrate on the opposite side and covering the opening of the core substrate and has thickness that is greater than thickness of the first resin insulating layer.
Inductor component and substrate with built-in inductor component
An inductor component includes a main body formed in a flat-plate shape and including a magnetic layer; an inductor wiring line disposed on a plane inside the main body; a first vertical wiring line that extends, from a pad portion which is an end portion of the inductor wiring line, in a first direction to pass through the inside of the main body, and is exposed on a first principal surface side of the main body; a second vertical wiring line that extends, from the pad portion of the inductor wiring line, in a second direction to pass through the inside of the main body, and is exposed on a second principal surface side of the main body; and an insulation layer of a non-magnetic body. The first vertical wiring line includes a via conductor and a columnar wiring line. The second vertical wiring line includes a columnar wiring line.
COMPOSITE WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
A composite wiring substrate includes a first wiring substrate including a first connection terminal, a second wiring substrate including a second connection terminal facing the first connection terminal, and a joint material joining the first connection terminal and the second connection terminal. The first outline of the first connection terminal is inside the second outline of the second connection terminal in a plan view. The joint material includes a first portion formed of an intermetallic alloy of copper and tin, and contacting each of the first connection terminal and the second connection terminal, and a second portion formed of an alloy of tin and bismuth, and including a portion between the first outline and the second outline in the plan view. The second portion contains the bismuth at a higher concentration than in the eutectic composition of a tin-bismuth alloy, and is separated from the second connection terminal.
WIRING BOARD
A wiring board includes an insulating base having a first principal surface, and a second principal surface opposite to the first principal surface, a first through hole formed in the base, a first conductive layer provided inside the first through hole, a first insulating layer covering the first principal surface, a second insulating layer covering the second principal surface, a second through hole formed in the first insulating layer, the base, and the second insulating layer, a magnetic material provided inside the second through hole, a third through hole famed in the magnetic material, and a second conductive layer provided inside the third through hole.
Carrier board structure with an increased core-layer trace area and method for manufacturing same
Carrier board structure with an increased core-layer trace area and method for manufacturing the same are introduced. The carrier board structure comprises a core layer structure, a first circuit build-up structure, and a second circuit build-up structure. The core layer structure comprises a core layer, a signal transmission portion, and an embedded circuit layer, wherein the signal transmission portion and the embedded circuit layer are disposed inside the core layer and electrically connected. The first circuit build-up structure is disposed on the core layer on a same side as the embedded circuit layer and is electrically connected to the embedded circuit layer. The second circuit build-up structure is disposed on the core layer on a same side as the signal transmission portion, and is electrically connected to the first circuit build-up structure through the signal transmission portion and the embedded circuit layer.
Printed circuit board and antenna module comprising the same
A printed circuit board and an antenna module including the same are provided. The printed circuit board includes a core layer; a first build-up structure disposed on an upper side of the core layer, including first insulating layers and first bonding layers, alternately stacked, and further including first wiring layers disposed on upper surfaces of the first insulating layers, respectively, and embedded in the first bonding layers, respectively; and a second build-up structure disposed on a lower side of the core layer, including second insulating layers and second bonding layers, alternately stacked, and further including second wiring layers disposed on lower surfaces of the second insulating layers, respectively, and embedded in the second bonding layers, respectively. The printed circuit board has a through-portion penetrating through the core layer and the second build-up structure, and has a region in which the through-portion is disposed as a flexible region.
WIRING BOARD
A wiring board according to the present disclosure includes a core insulating layer, a first laminated body located on an upper surface of the core insulating layer, and a second laminated body located on a lower surface of the core insulating layer. Each of the first laminated body and the second laminated body has a structure in which at least four electrical conductor layers and at least three build-up insulating layers are alternately located. The electrical conductor layers include two types, that are a first electrical conductor layer and a second electrical conductor layer. In the electrical conductor layers in the first laminated body, at least a first outermost layer and a first innermost layer are the first electrical conductor layers, and a first intermediate layer located farther from the core insulating layer than the first innermost layer includes at least two or more of the second electrical conductor layers.
LOCALIZED HIGH PERMEABILITY MAGNETIC REGIONS IN GLASS PATCH FOR ENHANCED POWER DELIVERY
Embodiments disclosed herein include electronic packages and methods of assembling such packages. In an embodiment, an electronic package comprises a core. In an embodiment the core comprises glass. In an embodiment, buildup layers are over the core, and a plug is embedded in the buildup layers. In an embodiment, the plug comprises a magnetic material. In an embodiment, an inductor wraps around the plug.
MANUFACTURING METHOD FOR PCB WITH THERMAL CONDUCTOR EMBEDDED THEREIN, AND PCB
A method for manufacturing a PCB with an embedded thermal conductor and a PCB are provided. A sheet of copper-clad ceramic serves as a thermal conductor. A sheet of copper foil having no opening serves as an outer layer of a laminate. A part of the sheet of copper foil covering the thermal conductor is removed after a lamination process, to expose a conductive layer as the outer layer of the thermal conductor. Finally, the outer layer pattern is formed. The sheet of copper foil has no opening before the lamination process, so that the sheet of copper foil has good flatness during the lamination process, thereby avoiding wrinkles. Moreover, the sheet of copper-clad ceramic serves as the thermal conductor, so that a pattern is manufactured on the outer layer of the thermal conductor based on the exposed conductive layer.
Asymmetric Stackup Structure for SoC Package Substrates
An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.