A component carrier includes a stack having an electrically conductive layer structure, with at least one recess, on an electrically insulating layer structure; a dielectric filling medium filling at least part of the at least one recess; and a further electrically insulating layer structure on the electrically conductive layer structure and on the dielectric filling medium. A method of manufacturing a component carrier includes forming a stack having an electrically conductive layer structure, with at least one recess, on an electrically insulating layer structure; at least partially filling the at least one recess by a dielectric filling medium; and thereafter forming a further electrically insulating layer structure on the electrically conductive layer structure and on the dielectric filling medium.

The present disclosure discloses a multilayer circuit board comprising a plurality of metal layers, a blind via and/or a buried via, the multilayer circuit board is capable of transmitting signal between the different metal layers. The blind via has a pad on a non-opening side of the blind via. An upper or lower layer metal layer on the non-opening side of the blind via adjacent to the blind via has a first hole which is located in a position corresponding to the pad on the non-opening side of the blind via in a depth direction of the blind via; and/or an upper and/or lower layer adjacent to the buried via has a second hole which is located in a position corresponding to the pad of an upper and/or lower orifice of the buried via in a depth direction of the buried via.

A wiring substrate having no core substrate includes a build-up layer including insulating layers and conductor layers such that the insulating layers include first, second, third and fourth insulating layers and that the conductor layers include a first conductor layer formed on the first insulating layer and a second conductor layer formed on the second insulating layer. The build-up layer has a first surface having the first insulating and first conductor layers, a second surface having the second insulating and second conductor layers, the third insulating layer formed on the first insulating layer on the opposite side of the first conductor layer, and the fourth insulating layer formed on the second insulating layer on the opposite side of the second conductor layer, and the build-up layer is formed such that the first and second insulating layers contain no core material and the third and fourth insulating layer include core material.

A semiconductor device includes: a substrate main body having a first surface and a second surface; an electric component arranged in the substrate main body; a surface conductor pattern arranged in a first circuit layer located on the second surface; a first internal conductor pattern and a second internal conductor pattern arranged in a second circuit layer located between the electric component and the second surface, and insulated from each other; at least one first heat conductor via extending from the electric component to the first internal conductor pattern; and at least one second heat conductor via extending from the surface conductor pattern to the second internal conductor pattern.

An apparatus is provided which comprises: a woven fiber layer, a first resin layer on a first surface of the woven fiber layer, a second resin layer on a second surface of the woven fiber layer, the second surface opposite the first surface, and the first and the second resin layers comprising cured resin, a third resin layer on the first resin layer, and a fourth resin layer on the second resin layer, the third and the fourth resin layers comprising an uncured resin, and wherein the fourth resin layer has a thickness greater than a thickness of the third resin layer. Other embodiments are also disclosed and claimed.

A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

A wiring substrate includes a multilayer core substrate including a core layer, core conductor layers, and core insulating layers, a first laminate formed on first surface of the substrate and including insulating layers and conductor layers such that each insulating layer includes resin without reinforcing material, and a second laminate formed on second surface of the substrate and including insulating layers and conductor layers such that each insulating layer includes resin without reinforcing material. The multilayer core substrate includes through-hole conductors penetrating through the core layer, and via conductors formed on the through-hole conductors and penetrating through the core insulating layers such that the through-hole conductors and via conductors connect outermost core conductor layers on the first and second surface sides, each of the core layer and core insulating layers includes insulating resin including reinforcing material, and the core layer has thickness greater than thickness of each core insulating layer.

An embedded component package structure including a dielectric structure, a semiconductor chip, a first polymer layer, and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure. The first polymer layer covers the semiconductor chip and has a first thickness, and the first thickness is greater than a second thickness of the dielectric structure above the first polymer layer. The patterned conductive layer covers an upper surface of the dielectric structure and extends over the first polymer layer, and the patterned conductive layer is electrically connected to the semiconductor chip.

Provided is a method for forming a through-hole including: forming a laminated body including a fluororesin layer having a first main surface and a second main surface, a first adhesive layer, a first reinforcing resin layer and a first conductor layer provided on the first main surface, a second adhesive layer, a second reinforcing resin layer and a second conductor layer provided on the second main surface; forming an opening in the first conductor layer and irradiating the opening with a laser beam to form a bottomed conduction hole with the second conductor layer exposed on a bottom surface of the conduction hole, wherein a thermal decomposition temperature of the second cured adhesive layer is lower than those of the first reinforcing resin layer and the second reinforcing resin layer, and a thickness of the second cured adhesive layer is 10 μm or more and 200 μm or less.

Structures that implement three-dimensional (3D) conductive material (e.g., copper) in printed circuit boards (PCBs) are disclosed. 3D (three-dimensional) conductive material may include trenches and/or buried vias that are filled with conductive material in the PCBs. Trenches may be formed in build-up layers of a PCB by overlapping multiple laser drilled vias. The trenches may be filled with conductive material using electroplating process(es). Buried vias may be formed through the core layers of the PCB by mechanical drilling. The buried via may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material. Various PCB structures are disclosed that implement combinations of these trenches and/or these buried vias filled with conductive material.