A component-embedded substrate includes: a plurality of insulating layers each including a wiring pattern formed on one surface; an embedded component including a connection terminal; and a plurality of vias that electrically connect the connection terminal to the wiring patterns adjacent to each other in a lamination direction. The plurality of insulating layers is laminated on the connection terminal. Each of the plurality of vias is composed of a via hole formed in the respective insulating layer of the plurality of the insulating layers and a conductive material provided in the via hole. One of the plurality of vias is a connection via directly connected to the connection terminal. Another of the plurality of vias is a first adjacent via adjacent to the connection via in the lamination direction. The first adjacent via is connected to the wiring pattern formed on a surface of a top insulating layer.

A multilayer electronic device may include a plurality of dielectric layers stacked in a Z-direction that is perpendicular to an X-Y plane. The device may include a first conductive layer overlying one of the plurality of dielectric layers. The multilayer electronic device may include a second conductive layer overlying another of the plurality of dielectric layers and spaced apart from the first conductive layer in the Z-direction. The second conductive layer may overlap the first conductive layer in the X-Y plane at an overlapping area to form a capacitor. The first conductive layer may have a pair of parallel edges at a boundary of the overlapping area and an offset edge within the overlapping area that is parallel with the pair of parallel edges. An offset distance between the offset edge and at least one of the pair of parallel edges may be less than about 500 microns.

A substrate is described with a thermal dissipation structure sintered to thermal vias. In one example, a microelectronic module includes a recess between first and second substrate surfaces. One or more thermal vias extend between the first substrate surface and the interior recess surface, wherein each of the thermal vias has an interior end exposed at the interior recess surface. A sintered metal layer is in the recess and in physical contact with the interior end of the thermal vias and a thermal dissipation structure is in the recess over the sintered metal layer. The thermal dissipation structure is attached to the substrate within the recess by the sintered metal layer, and the thermal dissipation structure is thermally coupled to the thermal vias through the sintered metal layer.

A package circuit structure includes a multilayer circuit board, an electronic component, and an insulating layer. The multilayer circuit board includes a metal portion and an opening. The opening is extending from a first side of the multilayer circuit board toward the second side of the multilayer circuit board facing the first side. A bottom of the opening is sealed by the metal portion. The electronic component is received in the opening and adhered to the metal portion. The electronic component is electrically connected to the multilayer circuit board and encapsulated in the opening by the insulating layer. A method for manufacturing the package circuit structure is also provided.

An integrated circuit chip carrier includes a wall surrounding a cavity. The wall includes one or more levels where each level is formed from a layer of a resin around a block. The block is made of a material different from the resin. The block is removed to open the cavity.

A package substrate according to an embodiment includes an insulating layer; a first outer circuit pattern disposed on an upper surface of the insulating layer; a second outer circuit pattern disposed under a lower surface of the insulating layer; a first connection portion disposed on an upper surface of a first-first circuit pattern of the first outer circuit pattern; a first contact portion disposed on the first connection portion; a first device disposed on the first connection portion through the first contact portion; a second contact portion disposed under a lower surface of a second-first circuit pattern of the second outer circuit pattern; a second device attached to the second-first circuit pattern through the second contact portion; and a second connection portion disposed under a lower surface of a second-second circuit pattern of the second outer circuit pattern; wherein the first connection portion is disposed with a first width and a first interval, and wherein the second connection portion is disposed with a second width greater than the first width and a second interval greater than the first interval.

A component carrier includes a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure; a barrier structure; and a component. The component has at least one pad embedded in the stack and/or in the barrier structure. At least a portion of one of the electrically conductive layer structure and the at least one pad includes copper in contact with the barrier structure.

A wiring substrate includes a first insulating layer with a first opening, a second insulating layer with a second opening, a high-frequency wiring layer, a first wiring layer, a second wiring layer, and a plurality of conductive pillars. The high-frequency wiring layer including a high-frequency trace is sandwiched between the first insulating layer and the second insulating layer. The first opening and the second opening expose two sides of the high-frequency trace respectively. The high-frequency trace has a smooth surface which is not covered by the first insulating layer and the second insulating layer and has the roughness ranging between 0.1 and 2 μm. The first insulating layer and the second insulating layer are all located between the first wiring layer and the second wiring layer. The conductive pillars are disposed in the second insulating layer and connected to the high-frequency trace.

A circuit board with improved heat dissipation function and a method for manufacturing the circuit board are provided. The method includes providing a first metal layer defining a first slot; forming a first adhesive layer in the first slot; electroplating copper on each first pillar to form a first heat conducting portion; forming a first insulating layer on the first adhesive layer having the first heat conducting portion, and defining a first blind hole in the first insulating layer; filling the first blind hole with thermoelectric separation metal to form a second heat conducting portion; forming a first wiring layer on the first insulating layer; forming a second insulating layer on the first wiring layer, defining a second blind hole on the second insulating layer; electroplating copper in the second blind hole to form a third heat conducting portion; mounting an electronic component on the second insulating layer.

A method for manufacturing a circuit board that includes a first electronic component and a circuit substrate is provided. The first electrode component includes two electrodes. The circuit substrate includes an inner substrate and an outer substrate formed on the inner substrate. The inner substrate defines a receiving cavity, and the first electronic component received in the receiving cavity. Each electrode faces an inner sidewall of the receiving cavity. The inner substrate includes a first insulating layer and a blocking layer embedded in the first insulating layer, an end of the blocking layer exposed from the inner sidewall. The outer substrate defines two through holes. Each through hole passes through a portion of the first insulating layer connected to the inner sidewall and exposes the blocking layer. A top end of each of the two electrodes facing the outer substrate is partially received in one through hole.