An electronic component module includes an electronic component, a resin structure body, a through wiring, a wiring layer, and a close-contact layer. The resin structure body covers at least a portion of the electronic component. The through wiring extends through the resin structure body. The wiring layer electrically connects the electronic component and the through wiring to each other. The close-contact layer is provided between the resin structure body and the through wiring and is in contact with the resin structure body and the through wiring. The close-contact layer includes an inorganic insulation film.

An electrical conductor includes a substrate; and a first conductive layer disposed on the substrate and including a plurality of metal oxide nanosheets, wherein adjacent metal oxide nanosheets of the plurality of metal oxide nanosheets contact to provide an electrically conductive path between the contacting metal oxide nanosheets, wherein the plurality of metal oxide nanosheets include an oxide of Re, V, Os, Ru, Ta, Ir, Nb, W, Ga, Mo, In, Cr, Rh, Mn, Co, Fe, or a combination thereof, and wherein the metal oxide nanosheets of the plurality of metal oxide nanosheets have an average lateral dimension of greater than or equal to about 1.1 micrometers. Also an electronic device including the electrical conductor, and a method of preparing the electrical conductor.

A laminate for printed wiring board is used in a method of manufacturing printed wiring boards that includes a process of forming a circuit by any one of a semi-additive method, a partly additive method, a modified semi-additive method, and an embedding method. The laminate includes an insulating resin substrate, a metal layer 1 and a metal layer 2 in this order. When a cross section that is parallel to the thickness direction of the laminate is processed by means of ion milling and the cross sections of the metal layer 1 and the metal layer 2 were observed with EBSD, each of the metal layer 1 and the metal layer 2 has one or plural crystal grain(s) at the processed cross section, and an area ratio of the total area of crystal grains of which a difference in angle of the <100> crystal direction from a perpendicular of the processed cross section is 15 or less from among the one or plural crystal grains to the total area of the plural crystal grains was 15% or higher but less than 97% in the metal layer 1 and the metal layer 2.

According to an embodiment, a flexible circuit board includes: a first substrate; a second substrate disposed on the first substrate and including an opening; a first conductive pattern part disposed on a bottom surface of the first substrate; a second conductive pattern part disposed on a top surface of the second substrate; a third conductive pattern part disposed between the first substrate and the second substrate; and an upper protective layer partially disposed on the second conductive pattern part and including a first open region, wherein the third conductive pattern part includes: a first inner lead pattern part disposed in the opening of the second substrate; and a first extension pattern part connected to the first inner lead pattern part, the second conductive pattern part includes: a second inner lead pattern part disposed in the first open region of the upper protective layer; and a second extension pattern part connected to the second inner lead pattern part, and a number of first inner lead pattern parts is greater than a number of second inner lead pattern parts.

A method for producing a foil arrangement includes structuring a conductive foil to be applied or applied onto a support foil upper side of a support foil and coating a conductive foil upper side of the structured conductive foil with a protective layer. A cover foil is laminated onto the support foil upper side and onto a protective layer upper side of the protective layer after the coating step.

Direct current plating methods inhibit void formation, reduce dimples and eliminate nodules. The method involves electroplating copper at a high current density followed by electroplating at a lower current density to fill through-holes.

A module board includes a substrate having a wire pattern on a surface, a protection layer covering the surface of the substrate so as to expose one edge region of the substrate surface, and a plurality of tab terminals connected to the wire pattern and arranged on one edge region. Each tab terminal has a width larger than a width of the wire pattern. Each tab terminal has a pattern layer. A protection layer is on the pattern layer at a region where each tab terminal is connected to the wire pattern, and a plating layer is on a remainder of the pattern layer.

A method for manufacturing a structure for embedding and packaging multiple devices by layer includes preparing a polymer supporting frame, mounting a first device in a first device placement mouth frame to form a first packaging layer, forming a first circuit layer and a second circuit layer, forming a second conductive copper pillar layer and a second sacrificial copper pillar layer, forming a second insulating layer on the first circuit layer, and forming a third insulating layer on the second circuit layer, forming a second device placement mouth frame vertically overlapped with the first device placement mouth frame, mounting a second device and a third device in the second device placement mouth frame to form a second packaging layer, forming a third circuit layer on the second insulating layer. A terminal of the second device and a terminal of the third device are respectively communicated with the third circuit layer.

A printed wiring board includes: an insulating base material; a first conductive layer disposed on a main surface of the insulating base material in a first region and a second region defined on a plane along the main surface; a second conductive layer disposed on a main surface of the first conductive layer in the first region; and an insulating layer disposed on the main surface of the first conductive layer in the second region. The ratio of a first evaluation value E1 to a second evaluation value E2 is 0.91 or more and 0.99 or less. The first evaluation value E1 is an evaluation value of strength of a first laminated part in the first region and the second evaluation value E2 is an evaluation value of strength of a second laminated part in the second region.

The present invention relates to an ink composition for light sintering, a wiring board using the same, and a method of fabricating the wiring board. The present invention aims to provide formation of a wiring pattern without damage to thin and soft wiring boards such as a flexible printed circuit board. The present invention provides an ink composition for light sintering including copper oxide nanoparticles having copper oxide films, a reducing agent for reducing copper oxidized by light irradiation to form copper nanoparticles, a dispersing agent, a binder, and a solvent.