An electronic component includes: a multilayer ceramic capacitor including a capacitor body and a pair of external electrodes, and an interposer including an interposer body having grooves and a pair of external terminals. Each of the external terminals includes a bonding portion, a mounting portion and a connection portion; and L=|A-A|/2 in which A is a distance from one end portion of the interposer in a length direction to one end portion of the multilayer ceramic capacitor in the length direction, A is a distance from the other end portion of the interposer in the length direction to the other end portion of the multilayer ceramic capacitor in the length direction, and L is an offset between the multilayer ceramic capacitor and the interposer in the length direction, and L/L0.100 in which L is a length of the multilayer ceramic capacitor.

A spacer is provided to allow a surface mount device (SMD) to be surface mounted onto a PCB with greater degrees of freedom. The spacer is designed to be surface mountable to the PCB and includes an electrically non-conducting body that has a first surface facing the SMD, a second surface facing the PCB, and through holes and/or indents in the electrically non-conducting body to accommodate electrical conductors that provide electrical connections between the SMD and the PCB. The spacer may provide one or more of: an elevated height (so that the SMD is elevated above the PCB), an offset along the surface of the PCB relative to a designated position for the SMD on the PCB, or a tilt in one or more directions relative to a surface of the PCB.

Disclosed embodiments include folded, top-to-bottom interconnects that couple a die side of an integrated-circuit package substrate, to a board as a complement to a ball-grid array for a flip-chip-mounted integrated-circuit die on the die side. The folded, top-to-bottom interconnect is in a molded frame that forms a perimeter around an infield to receive at least one flip-chip IC die. Power, ground and I/O interconnections shunt around the package substrate, and such shunting includes voltage regulation that need not be routed through the package substrate.

An electrical connector assembly includes a contact organizer having a substrate having a lower surface facing the host circuit board and an upper surface facing a component circuit board. The electrical connector includes data transmission contacts each including a main body, a upper mating element extending from the main body top mated to the component circuit board, and a lower mating element extending from the main body bottom soldered to the host circuit board. The main body includes a main body length between the top and the bottom and an adjustable height section to adjust a height of the main body between the top and the bottom. The adjustable height sections of the data transmission contacts are varied to adjust vertical positions of at least one of the upper mating element or the lower mating element such that the contacts have variable heights.

A display device includes: a display region; a frame region comprising a folding portion, the frame region being disposed around the display region; an outer terminal comprising a first outer terminal and a second outer terminal in the frame region, the first and second outer terminals being disposed sequentially on an outside in such a manner that the first outer terminal is closer to the display region than the second outer terminal is, the outside being more remote from the display region than the folding portion is; a first routing wire crossing the folding portion to electrically connect together the first outer terminal and an inner wire that is disposed in the display region; at least one inner terminal disposed inside the folding portion in the frame region; and a second routing wire that is flexible, the second routing wire electrically connecting at least the second outer terminal out of the first and second outer terminals to the at least one inner terminal without passing through the folding portion.

A display device includes a first substrate, a second substrate disposed on the first substrate, an image display layer disposed between the first substrate and the second substrate, a gate driver disposed at a first side surface of the first substrate, a data driver disposed at a second side surface of the first substrate, and conductive layers respectively disposed in recesses recessed from the first side surface of the first substrate. The gate driver is electrically connected to the conductive layers.

A high-frequency component includes a resin layer and a high-frequency circuit provided in and on the resin layer and includes an inductor and an electronic component. The electronic component is arranged on an upper surface of the resin layer. The inductor includes first and second metal pins provided such that upper end surfaces thereof are exposed from the upper surface of the resin layer and lower end surfaces thereof are exposed from a lower surface of the resin layer. The electronic component has a first outer electrode provided at a position superposed with the upper end surface of the first metal pin in plan view and is connected to the first metal pin, and a second outer electrode provided at a position superposed with the upper end surface of the second metal pin in plan view and is connected to the second metal pin.

A motherboard is provided. The motherboard includes a memory module, a processor and a memory slot. The memory module includes a first memory rank, a second memory rank, a plurality of first pins coupled to the first memory rank and a plurality of second pins coupled to the second memory rank. The processor includes a memory channel. The memory slot is coupled between the processor and the memory module, and is configured to transmit a first control signal from the memory channel to at least one of the plurality of first pins, or transmit a second control signal from the memory channel to at least one of the plurality of second pins. The first memory rank receives the first control signal through at least one of the plurality of first pins. The second memory rank receives the second control signal through at least one of the plurality of second pins.

According to one embodiment, a liquid crystal display device includes a liquid crystal panel and a backlight device. The backlight device includes a case with a bottom plate and a side plate, a light guide on the bottom plate, and a light source device. The light source device includes a wiring substrate and a light-emitting element on the wiring substrate. The wiring substrate includes a mounting portion on which the light-emitting element is mounted, a connection wiring portion on a back surface side of the bottom plate, and a joint portion which joints the mounting portion and the connection wiring portion together. The joint portion extends from an inside to an outside of the case through a gap between the side plate of the case and the liquid crystal panel.

Embodiments of a silicon heat-dissipation package for compact electronic devices are described. In one aspect, a device includes first and second silicon cover plates. The first silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The second silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The first primary side of the second silicon cover plate includes an indentation configured to accommodate an electronic device therein. The first primary side of the second silicon cover plate is configured to mate with the second primary side of the first silicon cover plate when the first silicon cover plate and the second silicon cover plate are joined together with the electronic device sandwiched therebetween.