A drill hole inspection method for using a drill hole inspection system to inspect a drill hole of a printed circuit board (PCB) is provided. The drill hole inspection method includes: scanning the PCB to obtain 3-dimensional (3D) image voxel data of the PCB; determining a first-dimension interval corresponding to the PCB along one direction of the 3D image voxel data; determining, in a plane of the 3D image voxel data which is orthogonal to the direction, a 2-dimensional (2D) position corresponding to the drill hole; extracting a portion of the 3D image voxel data as drill hole voxel data according to the first-dimension interval and the 2D position; analyzing the drill hole voxel data to obtain an inspection result of the drill hole; and outputting the inspection result through an output component. In addition, a drill hole inspection system and an inspection device using the same are also provided.

A circuit board includes: a first surface and a second surface opposite to the first surface; a through hole extending between the first surface and the second surface; a conductor covering an inner wall surface of the through hole, a first end and a second end of the conductor being terminated inside the through hole; and a wire connected to the conductor, wherein a sum of a length from a contact portion where the conductor contacts a connector pin inserted in the through hole to the first end of the conductor, and a length from a wire connecting portion where the conductor is connected to the wire to the second end of the conductor is 0.5 mm or less.

The disclosure provides a multilayer structure for a printed wiring board (PWB). The multilayer structure may include a plurality of insulating layers interleaved with a plurality of conductive layers comprising at least one inner conductive layer. The multilayer structure may also include one or more stub-less plated through-holes through the plurality of insulating layers and the plurality of conductive layers. The multilayer structure may include at least one secondary material layer formed on the at least one inner conductive layer. The secondary material layer defines a void that creates a discontinuity in the plated through-hole to achieve segmented metallization of the plated through-hole. The disclosure also provides a method of forming the multilayer structure.

A stub of a via formed in a printed circuit board is backdrilled to a predetermined depth. A capacitance probe is positioned within the via. Then the capacitance probe is used to obtain a test capacitance measurement. The test capacitance measurement is compared to a predetermined baseline capacitance measurement. Residual conductive plating material in the backdrilled stub causes the test capacitance measurement to exceed the predetermined baseline capacitance measurement. An indication is made that the predetermined baseline capacitance measurement has been exceeded.

An electrical break is created in a via that would ordinarily electrically connect different layers of a printed circuit board. The electrical break severs the via into two or more separate and electrically disconnected vias. The electrical break may be placed at any depth along the via, thus demarking different purposes associated with different layers.

The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.

A component carrier includes a stack with a plurality of electrically conductive layer structures and at least one electrically insulating layer structure. The electrically conductive layer structures include an electrically conductive vertical through-connection and a horizontally extending electrically conductive trace electrically coupled with an end portion of the vertical through-connection. A back-drill hole extends through at least part of the at least one electrically insulating layer structure towards the end portion of the vertical through-connection. An etching neck connects the back-drill hole with the end portion of the vertical through-connection.

Carrier board structure with an increased core-layer trace area and method for manufacturing the same are introduced. The carrier board structure comprises a core layer structure, a first circuit build-up structure, and a second circuit build-up structure. The core layer structure comprises a core layer, a signal transmission portion, and an embedded circuit layer, wherein the signal transmission portion and the embedded circuit layer are disposed inside the core layer and electrically connected. The first circuit build-up structure is disposed on the core layer on a same side as the embedded circuit layer and is electrically connected to the embedded circuit layer. The second circuit build-up structure is disposed on the core layer on a same side as the signal transmission portion, and is electrically connected to the first circuit build-up structure through the signal transmission portion and the embedded circuit layer.

A method for producing a printed circuit board is disclosed, In the method, a slot is formed in a substrate having at least three layers with the slot extending through at least two of the layers. The slot has a length and a width with the length being greater than the width. The sidewall of the substrate surrounding the slot is coated with a conductive layer. Then, the conductive layer is separated into at least two segments that are electrically isolated along the side wall of the substrate.

One embodiment can provide a method and system for compensating for timing skew in a differential pair transmission line on a printed circuit board (PCB). During operation, the system obtains a PCB comprising one or more layers and at least a differential pair transmission line. The differential pair transmission line comprises first and second transmission lines, with a respective transmission line coupled to at least one via extending through the one or more layers of the PCB. The system determines a difference in length between first and second transmission lines and determines a stub length of the at least one via based on the determined difference in length between the first and second transmission lines, thereby compensating for the time skew in the differential pair transmission line.