H05K2203/0207

POWER VIA RESONANCE SUPPRESSION
20240098898 · 2024-03-21 ·

One aspect provides a printed circuit board (PCB). The PCB can include a plurality of layers and a plurality of plated through-hole (PTH) vias extending through the plurality of layers. The plurality of layers can include at least a top layer for mounting components, a second surface layer, and a first power layer positioned between the top layer and the second surface layer. The plurality of PTH vias can include at least one power via coupled to the first power layer to provide power to components mounted on the top layer. A stub length of the power via can be less than a distance between the power layer and the second surface layer.

SYSTEM AND METHOD TO ELIMINATE VIA STRIPING
20240080978 · 2024-03-07 ·

A printed circuit board includes metal layers, a metalized circuit via interconnecting a first one of the metal layers and a second one of the metal layers, and a back-drill hole drilled to remove metalization of the circuit via from a third metal layer adjacent to the second metal layer to a fourth metal layer at a first surface of the printed circuit board. The back-drill hole has a profile that includes a first undercut at a bottom of the first back-drill hole.

CIRCUIT BOARD STRUCTURE AND METHOD FOR FORMING THE SAME
20240114632 · 2024-04-04 · ·

A circuit board structure is provided. The circuit board structure includes a via hole, a conductive layer, and an alternate stacking of a plurality of circuit layers and a plurality of insulating layers. The via hole penetrates through the plurality of circuit layers and the plurality of insulating layers. The lateral ends of the plurality of insulating layers form the sidewall of the via hole. The conductive layer is conformally disposed within the via hole. The conductive layer exposes the first region of the sidewall and covers the second region of the sidewall. The sidewall extends in the longitudinal direction of the via hole and has no misalignments in the radial direction.

CIRCUIT BOARD AND BACK DRILLING PROCESSING METHOD
20240114625 · 2024-04-04 ·

A back drilling processing method for a circuit board includes: obtaining a board to be back drilled, wherein the board includes a target signal layer and at least two conductive reference layers; drilling a through hole at a set position of the board, and obtaining an actually measured spacing between two conductive reference layers; in response to a hole to be back drilled being of a first type, determining a target back drilling depth; controlling a drilling bit to drill for the target back drilling depth towards the target signal layer; in response to the hole to be back drilled being of a second type, determining a target relative height of a back drilling end point relative to a machine; and controlling the drilling bit to drill for the target relative height towards the target signal layer. The back drilling does not drill through the target signal layer.

Single ended vias with shared voids

An electronic device includes a printed circuit board. The printed circuit board includes a plurality of different signaling planes and a plurality of different reference planes. A single ended via interconnects the plurality of different signaling planes. A return via interconnects the plurality of different reference planes. The electronic device includes a shared void that includes the single ended via and the return via.

Machining station and method for machining workpieces

The disclosure relates to a machining station for machining platelike workpieces (1) by means of at least one tool (10, 13, 14). The machining station has a measuring device (16) for acquiring data relating to the position of bores, a drill (10, 13, 14) for generating bores in the workpiece (1), and a data processor (17) for processing data of the at least one measuring device (16) and/or for controlling the at least one drill (10, 13, 14). The data processor (17) is here suitable and set up for performing an adjustment between a desired drilling position and/or a desired bore depth and an actual position and/or actual depth as determined by the at least one measuring device (16) for a bore present in the workpiece (1), and adapting the drilling position and/or bore depth for generating bores by means of the at least one drill (10, 13, 14).

PRINTED WIRING BOARD AND MANUFACTURING METHOD FOR PRINTED WIRING BOARD
20240121903 · 2024-04-11 · ·

To improve the peel strength of a wiring pattern formed at a cavity bottom portion while enabling connection between an electronic component inside a cavity and a circuit outside the cavity to be performed at the cavity bottom portion. A method of manufacturing a printed wiring board according to the present disclosure includes performing pattern plating on a substrate made of insulating resin. Forming an electrical conductor layer on a seed layer of a second face, forming a first insulating resin layer on a first face and forming a second insulating resin layer. Drilling in and removing the insulating resin to form a cavity. Removing, by laser machining, a remaining portion of the substrate in the cavity and exposing a surface position of the second insulating resin layer to be equivalent to a surface position of the electrical conductor layer embedded in the second insulating resin layer.

Clearance size reduction for backdrilled differential vias

A printed circuit board (PCB) may include a plurality of horizontally disposed signal layers. The PCB may include a first vertically disposed differential via electrically connected to a first horizontally disposed signal layer, of the plurality of horizontally disposed signal layers, and a second horizontally disposed signal layer of the plurality of horizontally disposed signal layers. The PCB may include a second vertically disposed differential via electrically connected to the first signal horizontally disposed layer and the second horizontally disposed signal layer. The PCB may include a first set of clearances encompassing the first vertically disposed differential via and the second vertically disposed differential via, a second set of clearances encompassing the first vertically disposed stub, and a third set of clearances encompassing the second vertically disposed stub.

Back-drilled through-hole printed circuit board (PCB) systems
10426042 · 2019-09-24 · ·

An approach for through-hole component soldering for a PCB, and a resulting PCB assembly, that eliminates protruding solder joints, is provided. The approach comprises back-drilling, from a bottom surface of a PCB, one or more through-holes, wherein each back-drilled through-hole is back-drilled to a depth partially through the PCB and at a diameter that is larger than the diameter of the through hole. Solder paste is applied to the PCB. The components are placed on the PCB, inserting each pin into a corresponding through-hole. The PCB is passed through a solder process, whereby, within each through-hole having a component pin inserted therein, the solder paste is wicked into the through-hole, and forms a solder joint with the respective pin. Each solder joint of a back-drilled through-hole is situated within the through-hole in a manner whereby the solder joint does not protrude beyond the bottom surface of the PCB.

Printed Circuit Board Having Vias Arranged for High Speed Serial Differential Pair Data Links

A printed circuit board includes a differential signal via pairs to route differential signal between layers of the printed circuit board. A first differential signal via pair is oriented in a first orientation and a second differential signal via pair is oriented perpendicular to the first orientation. The second differential signal via pair is located such that a midpoint of a first line segment drawn between centers of first and second vias of the second differential signal pair intersects a first ray drawn from a center of a first via of the first differential signal via pair through a center of a second via of the first differential signal via pair. Further, the second differential signal via pair is located such that the midpoint of the first line segment is at a characteristic via-to-via pitch distance for the printed circuit board from the center of the second via of the first differential signal via pair.