Examples of semiconductor packages with stacked RDLs described herein may include, for example, a first RDL comprising multiple RDL layers coupled to a second RDL comprising multiple RDL layers using copper pillars and an underfill in place of a conventional substrate. The examples herein may use RDLs instead of substrates to achieve smaller design feature size (x, y dimensions reduction), thinner copper layers and less metal usage (z dimension reduction), flexibility to attach semiconductor dies and surface mount devices (SMD) on either side of the package, and less number of built-up RDL layers.

Methods include receiving at least one electronic device including a sensor or an emitter, placing a cover over the sensor or emitter, placing the electronic device, including the cover, into a transfer mold system, encapsulating the electronic device with charge material, and removing a portion of the encapsulating charge material and the cover to expose the sensor or emitter to the environment.

A circuit carrier board includes a first build-up layer structure, a substrate, an adhesive layer, and a conductive structure. The first build-up layer includes a plurality of first dielectric layers and a plurality of first circuit layers original stacked. The substrate includes a base and a second build-up layer structure disposed on the base. The second build-up layer structure includes a plurality of second dielectric layers and a plurality of second circuit layer original stacked. A top most layer of the second circuit layers is exposed outside of the second dielectric layers. The conductive structure penetrates through the first dielectric layers, the first circuit layers and the adhesive layer, and contacts with the top most layer of the second circuit layers. The conductive structure electrical connects the first circuit layers to the second circuit layers. A manufacturing method of the circuit carrier board is also provided.

Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.

A printed circuit board is provided. The printed circuit board includes an insulating material, and a circuit comprising a first region that partially penetrates the insulating material, and a second region formed on the first region and that protrudes from an upper portion of the insulating material, the first region includes a first electroplating layer and a first electroless plating layer that are formed between the insulating material and the first electroplating layer.

An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.

Systems and processes for recycling printed circuit boards, wherein precious metals may be reclaimed. The system generally includes a number of modules to systematically remove materials from the printed circuit boards and to separate the precious metals from the materials.

A circuit board is formed from a catalytic laminate having a resin rich surface with catalytic particles dispersed below a surface exclusion depth. The catalytic laminate is subjected to a drilling and blanket surface plasma etch operation to expose the catalytic particles, followed by an electroless plating operation which deposits a thin layer of conductive material on the surface. A photo-masking step follows to define circuit traces, after which an electro-plating deposition occurs, followed by a resist strip operation and a quick etch to remove electroless copper which was previously covered by photoresist.

A method for fabricating an assemble substrate is provided, including stacking a circuit portion on a plurality of circuit members. The circuit members are spaced apart from one another in a current packaging process to increase a layer area. The assemble substrate thus fabricated meets the requirements for a packaging substrate of a large size, and has a high yield and low fabrication cost.

A printed circuit board includes an insulating layer including a cavity including a groove structure formed on one surface of the insulating layer, a circuit pattern including a first pad formed on a bottom surface of the cavity and a second pad formed inside the insulating layer, a first metal layer embedded in a side surface of the cavity, the first metal layer being in contact with the bottom surface of the cavity and being formed along the boundary of the cavity, and a second metal layer formed on the second pad and having a stepped structure formed with the second pad.