Patent classifications
H05K2203/0307
PCB transmission lines having reduced loss
Signal transmission structures within a printed circuit are formed to have reduced loss by making specific accommodations to reduce the surface roughness of an adjacent power plane, and thereby reducing the effects of magnetically induced currents. The power plane structure will retain sufficient surface roughness to accommodate manufacturing operations, while also contributing to reduced signal transmission losses in the adjacent signal transmission structure. The transmission structures thereby being capable of more efficiently transmitting high speed signals without undesired attenuation and loss.
METHOD FOR PRODUCING A PRINTED WIRING BOARD
A present invention provides a method for manufacturing a printed wiring board having excellent plating adhesion to a resin substrate having low surface roughness such as having surface roughness Ra of 0.2 m or less, having excellent treating solution stability, and having high penetrability into the resin substrate. The method for manufacturing a resin substrate includes a step 1A or a step 1B; and a step 2 after the step 1A or the step 1B; and the steps are conducted before conducting electroless plating.
FIBER OPTICS PRINTED CIRCUIT BOARD ASSEMBLY SURFACE CLEANING AND ROUGHENING
The present disclosure generally relates to printed circuit boards or printed circuit board assemblies for fiber optic communications. In one example, an optoelectronic assembly may include a printed circuit board including a laser-roughened area, at least one optoelectronic component coupled to a surface of the printed circuit board, and an optical component attached to the printed circuit board. The coupling area may be defined by the optical component contacting the printed circuit board, and the laser-roughened area may be positioned entirely within the coupling area defined by the optical component contacting the printed circuit board.
Printed circuit board and method for manufacturing printed circuit board
The present invention relates to a printed circuit board embedding a power die wherein interconnections between the power die and the printed circuit board are composed of micro/nano wires, the printed circuit board comprising a cavity wherein the power die is placed, and wherein the cavity is further filled with a dielectric fluid.
MULTILAYER SUBSTRATE AND ANTENNA ELEMENT
The insertion loss of a multilayer substrate and an antenna element is reduced. A multilayer substrate according to an embodiment of the present disclosure includes a multilayer body, a wire conductor, and a first ground electrode. The multilayer body is formed by dielectric layers being layered. The wire conductor is formed in the multilayer body, and a radio frequency signal passes through the wire conductor. The first ground electrode is formed in or on the multilayer body and includes a first surface that faces the wire conductor. The first surface includes a first region and a second region. The surface roughness of the first region is lower than the surface roughness of the second region. The first region overlaps at least part of the wire conductor in plan view in a direction normal to the first ground electrode.
Fiber optics printed circuit board assembly surface cleaning and roughening
The present disclosure generally relates to printed circuit boards or printed circuit board assemblies for fiber optic communications. In one example, a method may include coupling at least one optoelectronic component to a surface of a printed circuit board. The method may include lasering the surface of the printed circuit board to form a laser-roughened area on the surface of the printed circuit board. The method may include coupling an optical component to the printed circuit board at the laser-roughened area on the surface of the printed circuit board.
METHOD FOR MANUFACTURING COPPER FOIL FOR HIGH FREQUENCY CIRCUIT
A method of manufacturing a copper foil for a high frequency circuit includes sequentially forming a fine roughness copper nodule layer on a surface of an electroplated copper layer, the fine roughness copper nodule layer being consisted essentially of copper particles or copper alloy particles with a particle size of 100 nm to 200 nm; then, performing electroplating with a ZnNi co-electroplating formula for 3 seconds or more to form a ZnNi plating layer on the fine roughness copper nodule layer, the ZnNi plating layer including 90-150 g/dm.sup.2 of zinc and 75-120 g/dm.sup.2 of nickel; forming a rust-proof layer on the ZnNi plating layer, the rust-proof layer including 20-40 g/dm.sup.2 of chromium; and next, forming a hydrophobic layer on the rust-proof layer, the hydrophobic layer having a water contact angle of 80 to 150 degrees.
Method for Producing Film Formation Substrate, Film Formation Substrate, and Surface Treatment Agent
An object is to provide, for example, a method for manufacturing a film-forming substrate that can sufficiently improve both bleeding of a resin composition and adhesion between the resin composition and a metal substrate surface. For example, provided is a method for manufacturing a film-forming substrate having a film of a resin composition formed on a metal substrate surface, the method including: an etching step of etching a metal substrate surface with a micro-etching agent; a surface treatment step of bringing the etched metal substrate surface into contact with a surface treatment agent to perform a surface treatment such that a contact angle of water on the surface is 50 or more and 150 or less; and a film forming step of forming a film of a resin composition on the surface-treated metal substrate surface by an inkjet method.
SUBSTRATE FOR MOUNTING SEMICONDUCTOR ELEMENT
A substrate for mounting a semiconductor element thereon includes a metal plate and columnar terminal portions composed only of plating layers and formed on one-side surface of the metal plate. The columnar terminal portions include, as an outermost plating layer, a roughened silver plating layer having acicular projections. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111> and <101>. The substrate for mounting a semiconductor element thereon can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer, which are to serve as terminals and the like, to be thin.
COPPER INTERFACE FEATURES FOR HIGH SPEED INTERCONNECT APPLICATIONS
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first layer of a package substrate and a conductive trace over the first layer of the package substrate. In an embodiment, the conductive trace comprises a conductive body with a first surface over the first layer of the package substrate, a second surface opposite the first surface, and sidewall surfaces coupling the first surface to the second surface. In an embodiment, the second surface has a first roughness and the sidewall surfaces have a second roughness that is less than the first roughness.