The present invention relates to a method of producing a ceramic substrate, the method including: joining a metal layer to each of opposite surfaces of a ceramic base material; forming, on the metal layers, a first electrode layer and a second electrode layer having a larger volume than the first electrode layer; calculating the volumes of the first and second electrode layers; and controlling a thickness of the second electrode layer, thereby controlling warpage which may occur due to a difference between the volumes of the first and second electrode layers. The present invention can reduce the defect rate of a ceramic substrate by controlling warpage that may occur due to the difference in volume taken up by the metal layers on the opposite surfaces of the base material.

The present publication discloses a circuit-board structure, including a conductor layer on an insulating material layer, and a conductor pattern on top of the conductor foil. A component is attached to the conductor foil and the conductor pattern, the component embedded at least in part in adhesive which attaches the component to the insulating material layer. A recess is formed in the conductor foil and the insulating material layer, and contact openings are in the insulating material layer at locations of contact areas of the component. Conductor material of the conductor foil is not present outside the conductor pattern, and the conductor foil is located between the conductor pattern and the insulating material layer.

Provided herein are methods for manufacturing a multilayer circuit structure having embedded circuits and the multilayer circuit structure made thereby. A substrate having at least one existing circuit on the surface is provided, then a dielectric layer is formed to cover the existing circuit. A metal layer is subsequently formed on the dielectric layer. The metal layer is made into a metal hard mask with a pattern by photoimaging, then the pattern is transferred to the dielectric layer underneath by plasma etching to create trenches and pads for vias at the same time. After vias are made on the pads, a conductive metal is deposited into the trenches and vias to form an embedded trace layer in the respective dielectric layer. The excess conductive metal is removed to obtain a new circuit embedded in the dielectric layer and is coplanar with the surface of the dielectric layer.

The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.

A single-layer redistribution plate functioning as a space translator between a device under testing (“DUT”) and a testing PCB may comprise a hard ceramic plate. A DUT side of the plate may have pads configured to interface with a device under testing. Both sides of the plate may comprise traces, vias, and pads to fan out the DUT pad pattern so that the plate side opposite the DUT side has spatially translated pads configured to interface with the pads on a testing PCB. Fabricating a redistribution plate may comprise calibrating and aligning, laser milling vias, laser milling trenches and pads, copper plating, grinding and polishing, removing residual copper, and coating the copper surfaces.

A wiring board manufacturing method includes: forming a first groove structure in a first principal surface of a base by scanning with laser light in a first irradiation pattern such that the first groove structure has a first width; irradiating an inside of the first groove structure with laser light in a second irradiation pattern that is different from the first irradiation pattern to form recessed portions inside the first groove structure; and forming a first wiring pattern by filling the first groove structure with a first electrically-conductive material to form a first wiring pattern whose shape matches with a shape of the first groove structure in a top view.

An extremely thin copper foil is provided that enables formation of highly fine different wiring patterns with a line/space (L/S) of 10 μm or less/10 μm or less on two sides of the copper foil and is thus usable as an inexpensive and readily processable substitution for silicon and glass interposers. The extremely thin copper foil includes, in sequence, a first extremely thin copper layer, an etching stopper layer, and the second extremely thin copper layer. Two sides of the extremely thin copper foil each have an arithmetic average roughness Ra of 20 nm or less.

The present invention relates to a method of producing a ceramic substrate, the method including: joining a metal layer to each of opposite surfaces of a ceramic base material; forming, on the metal layers, a first electrode layer and a second electrode layer having a larger volume than the first electrode layer; calculating the volumes of the first and second electrode layers; and controlling a thickness of the second electrode layer, thereby controlling warpage which may occur due to a difference between the volumes of the first and second electrode layers. The present invention can reduce the defect rate of a ceramic substrate by controlling warpage that may occur due to the difference in volume taken up by the metal layers on the opposite surfaces of the base material.

A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.

A resin multilayer substrate includes a first resin layer including a thermoplastic resin as a main material, a second resin layer including the thermoplastic resin as a main material and superposed on the first resin layer, a first interlayer-connection conductor passing through the first resin layer in a thickness direction, and a first conductor pattern at an area including a region in which the first interlayer-connection conductor is exposed at the surface of the first resin layer between the first resin layer and the second resin layer. The first conductor pattern includes a portion in or at which a portion of the first interlayer-connection conductor is disposed. The first conductor pattern includes a first portion covering the region exposed at the surface of the first resin layer; and a second portion disposed surrounding the first portion. The first portion and the second portion have different thicknesses from each other.