A flexible wiring circuit board includes a first insulating layer, a wire disposed at one side in a thickness direction of the first insulating layer, a second insulating layer disposed at one side in the thickness direction of the wire, a shield layer disposed at one side in the thickness direction of the second insulating layer, and a third insulating layer disposed at one side in the thickness direction of the shield layer. The shield layer includes an electrically conductive layer and two barrier layers sandwiching the electrically conductive layer therebetween in the thickness direction. The electrically conductive layer is selected from a metal belonging to a group 11, and the fourth period and the fifth period in the periodic table, and the barrier layer is selected from a metal belonging to groups 4 to 10, and the fourth to the sixth periods in the periodic table.

A circuit board includes a first wiring layer and a build-up structure. The build-up structure includes at least one dielectric layer and at least one second wiring layer. Each dielectric layer and each second wiring layer are alternately arranged. The at least one dielectric layer comprises an outermost dielectric layer. The at least one second wiring layer is formed on a side of the outermost dielectric layer, and comprises an outermost second wiring layer. A portion of the first wiring layer is embedded in a side of the outermost dielectric layer facing away the outermost second wiring layer, a remaining portion of the first wiring layer protrudes from the outermost dielectric layer. A method for manufacturing a circuit board is provided.

In a printed wiring board, when a plurality of wiring base bodies are collectively stacked, a constituent material of a first layer of an insulating resin film has a low melting point, so that the first layer is easily melted. Therefore, thermal welding on an upper surface of the wiring base body is reliably performed, and the wiring base bodies are bonded to each other with high reliability.

A process for forming a graphene circuit pattern on an object is described. A graphene layer is grown on a metal foil. A bonding layer is formed on a protective film and a surface of the bonding layer is roughened. The graphene layer is transferred onto the roughened surface of the bonding layer. The protective film is removed and the bonding layer is laminated to a first core dielectric substrate. The metal foil is etched away. Thereafter the graphene layer is etched using oxygen plasma etching to form graphene circuits on the first core dielectric substrate. The first core dielectric substrate having graphene circuits thereon is bonded together with a second core dielectric substrate wherein the graphene circuits are on a side facing the second core dielectric substrate wherein an air gap is left there between.

Provided herein is a carrier-attached copper foil having desirable fine circuit formability. The carrier-attached copper foil includes a carrier, an interlayer, and an ultrathin copper layer in this order, wherein D2D1 is 0.30 to 3.83 m, where D1 is the gravimetrically measured thickness of the carrier-attached copper foil excluding the carrier and the interlayer, and D2 is the maximum thickness of the layer remaining on a bismaleimide-triazine resin substrate in case of detaching the carrier after the carrier-attached copper foil is laminated to the resin substrate from the ultrathin copper layer side by being heat pressed under a pressure of 20 kgf/cm.sup.2 at 220 C. for 2 hours.

A wiring substrate includes an insulating layer, a connection pad buried in the insulating layer in a state that an upper surface of the connection pad is exposed from an upper surface of the insulating layer and a lower surface and at least a part of a side surface of the connection pad contact the insulating layer, and a concave level difference portion formed in the insulating layer around an outer periphery part of the connection pad, wherein an upper surface of the connection pad and an upper surface of the insulating layer are arranged at a same height.

A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening communicating the cavity and a pad of the first patterned circuit layer is located in the opening. A hole diameter of the opening is smaller than a hole diameter of cavity. An inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference.

A process for forming a graphene circuit pattern on an object is described. A graphene layer is grown on a metal foil. A bonding layer is formed on a protective film and a surface of the bonding layer is roughened. The graphene layer is transferred onto the roughened surface of the bonding layer. The protective film is removed and the bonding layer is laminated to a first core dielectric substrate. The metal foil is etched away. Thereafter the graphene layer is etched using oxygen plasma etching to form graphene circuits on the first core dielectric substrate. The first core dielectric substrate having graphene circuits thereon is bonded together with a second core dielectric substrate wherein the graphene circuits are on a side facing the second core dielectric substrate wherein an air gap is left there between.

Disclosed is a surface treated copper foil in which the dropping of the roughening particles from the roughening treatment layer provided on the surface of the copper foil is favorably suppressed.

Also disclosed is a surface treated copper foil, comprising a copper foil, a roughening treatment layer on one surface, and/or another roughening treatment layer the other surface of the copper foil, wherein a height of roughening particles of the roughening treatment layer is 5 to 1000 nm from the surface, a color difference ?E*ab according to JIS Z 8730 of a surface of a side of the roughening treatment layer is 65 or less, and a glossiness of the TD of the surface of the side of the roughening treatment layer is 70% or less.

A manufacturing method for a printed circuit board includes: transferring roughness of a metal film to an insulating layer by laminating the metal film on the insulating layer, the metal film having the roughness formed on one surface thereof and having a discrete metal layer laminated thereon; exposing a surface of the insulating layer, on which the roughness is transferred, by removing the metal film; processing the surface of the insulating layer having the roughness formed thereon with an acidic solution; and forming a circuit pattern on the insulating layer by a plating process.