An electronic device package includes: a substrate including a central region, and a first side region and a second side region at opposite sides of the central region; a first component in the first side region or the second side region, the first component having a first height above a surface of the substrate; a second component in the central region, the second component having a second height above the surface of the substrate that is lower than the first height; a reinforcement member in the central region and overlapping the second component, the reinforcement member having a third height above the surface of the substrate that is lower than the first height and higher than the second height; and an encapsulation member covering the first component and the second component.

A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.

Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.

A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.

There is provided a method for implementing an electronic card. The method can include providing the electronic card with a printed circuit board. The method further includes selecting one of a first side and a second side as a specified side on which only connection hardware is to be mounted. The first side is located at a first x-y plane and the second side is located at a second x-y plane, the first and second x-y planes being separated by a length equal to a thickness of the PCB. The first and second x-y planes are parallel.

A flexible circuit film includes the following elements: a base film; a first power input terminal, a second power input terminal, a first power output terminal, and a second power output terminal each disposed on the base film; an integrated circuit chip disposed between the first power input terminal and the first power output terminal and overlapping the base film; first power wiring disposed on the base film, connecting the first power input terminal to the first power output terminal, and including a first connection part; and second power wiring disposed on the base film, connecting the second power input terminal to the second power output terminal, and including a second connection part. The first connection part and the second connection part are disposed between the base film and the integrated circuit chip, overlap the integrated circuit chip, and are spaced from each other.

A device and substrate are disclosed. An illustrative device includes a substrate having a first surface and an opposing second surface, a solder material receiving curved surface exposed at the second surface of the substrate, a solder resist material that at least partially covers the solder material receiving curved surface such that a middle portion of the solder receiving curved surface is exposed and such that an edge portion of the solder material receiving curved surface is covered by the solder resist material and forms an undercut, and a solder material disposed within the solder material receiving curved surface and within the undercut.

A hermetic glass module for wireless communication. In some embodiments, the module may comprise a plurality of glass layers comprising a first layer having capacitors, inductors, and resonators, a second layer comprising capacitors, inductors, diplexers, and waveguides, a third layer comprising microchips, and capacitors, and a fourth layer comprising a glass cover layer, and antennas disposed within the glass cover layer. The plurality of glass layers may each be separated by a substrate of a plurality of substrates and are connected by a redistribution layer (RDL) of a plurality of RDLs.

A first board includes a first ground plane, a first ground land, a first transmission line, and a first signal land connected to the first transmission line, wherein the first ground land and the first signal land are formed on the same surface. A second board includes a second ground plane, a second ground land, a second transmission line, and a second signal land connected to the second transmission line, wherein the second ground land and the second signal land are formed on a surface opposing the first board. The second ground land and the second signal land oppose the first ground land and the first signal land, respectively. A conduction member connects the first ground land and the second ground land. The first signal land and the second signal land are connected by capacitance coupling without using any conductor.

A first board includes a first ground plane, a first ground land, a first transmission line, and a first signal land connected to the first transmission line, wherein the first ground land and the first signal land are formed on the same surface. A second board includes a second ground plane, a second ground land, a second transmission line, and a second signal land connected to the second transmission line, wherein the second ground land and the second signal land are formed on a surface opposing the first board. The second ground land and the second signal land oppose the first ground land and the first signal land, respectively. A conduction member connects the first ground land and the second ground land. The first signal land and the second signal land are connected by capacitance coupling without using any conductor.