A semiconductor device includes a semiconductor unit, a printed circuit board and a case, including a bottom portion formed in a plate-like shape and a side wall portion surrounding an outer periphery of the bottom portion of the case. The bottom portion has a main circuit area having an opening, and a control circuit area adjacent to the main circuit area in a plan view. The semiconductor unit is attached in the main circuit area from a rear surface of the bottom portion such that an insulating plate of the semiconductor unit is exposed to inside the case through the opening. The printed circuit board is disposed in the control circuit area on the front surface of the bottom portion via a spacer, having a gap between the printed circuit board and the front surface of the bottom portion.

A method of improving electrical interconnections between two electrical is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta-material overlay provide, the enhancements for conventional discrete wire bonds whilst also facilitating single integrated designs compatible with tape implementation.

An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.

In an embodiment a LED chip insert for a printed circuit board includes a lead frame in which a number of electrically conductive strings with respective ends are formed by punching, the strings having support surfaces which are configured for mounting on the printed circuit board and which form a common plane, wherein the lead frame has a region formed as a recess with respect to the ends, an injection molded frame including an electrically insulating material and annularly surrounding a surface of the lead frame exposed within the region formed as the recess facing the ends of the strings, and thereby effecting an overall trough-like structure; and at least one LED chip which is placed in the region formed as the recess and has a first electrical contact terminal and a second electrical contact terminal, the first electrical contact terminal being electrically conductively connected to a first one of the strings and the second electrical contact terminal being electrically conductively connected to a second one of the strings.

An optical transceiver includes a housing, a mother board, an optical communication module and a daughter board. The mother board is accommodated in the housing. The optical communication module is disposed on a top surface of the mother board, and the optical communication module includes a first electrical interface. The daughter board is disposed on the top surface of the mother board, and the daughter board includes a second electrical interface electrically connected with the first electrical interface. The optical communication module is disposed on a flat region of the top surface of the mother board.

The invention relates to a power electronics module including a first circuit carrier (5,10, 11), as well as an electronic assembly (20, 30) arranged in an electrically contacting manner on the upper flat side of the first circuit carrier (5, 10, 11), and a first cooling element (40) in thermal contact with the underside of the first circuit carrier (5, 10, 11), wherein the module has at least one second assembly (20, 30) arranged on the upper side of a second circuit carrier (5, 10, 11) and a second cooling element (40) arranged on the underside of the second circuit carrier (5, 10, 11), wherein the first and the second circuit carriers (5, 10, 11) are arranged with their upper sides facing one another and at least one central heat sink (60, 61, 63, 64) that is electrically insulated from the assemblies (20, 30) is arranged in the space between the assemblies (20, 30), wherein the assemblies (20, 30) and the at least one central heat sink (60, 61, 63, 64) are embedded in a heat-conducting potting compound (50), wherein the module has a number N≥3 of circuit carriers (5, 10, 11) with assemblies (20, 30) mounted on their upper sides and cooling elements (40) mounted on their undersides, and the sides having the assemblies (20, 30) and directed towards one another are arranged around the central heat sink (60, 61, 63, 64) forming a shape with an N-sided polygon as across-section.

In an embodiment a sensor element includes a carrier having an electrically insulating material, a top side and a bottom side, an NTC thermistor arranged on the top side of the carrier and at least two first electrodes configured for electrically contacting the sensor element, wherein the first electrodes are arranged on the top side of the carrier, wherein the sensor element is configured to measure a temperature, and wherein the sensor element is configured for direct integration in an electrically insulating manner.

A memory card comprising a first main surface and a second main surface opposing each other, and including a printed circuit board (PCB) constituting the first main surface, the PCB including a plurality of first external connection terminals, the plurality of first external connection terminals exposed on the first main surface, a plurality of memory devices stacked on the PCB, a memory controller configured to control the plurality of memory devices, a molding layer encapsulating the plurality of memory devices and the memory controller, the molding layer constituting the second main surface, and one or more second external connection terminals electrically connected to the memory controller, the one or more second external connection terminals embedded in the molding layer and exposed by the molding layer on the second main surface may be provided.

The present application relates to a photosensitive assembly, including a circuit board, a photosensitive chip and a metal wire. A first surface of the circuit board has a protrusion structure and a chip attachment area, and the protrusion structure is distributed in the chip attachment area. The photosensitive chip is attached to the first surface by an adhesive, and the adhesive is at least disposed between the top surface of the protrusion structure and the bottom surface of the photosensitive chip. The metal wire electrically connects the photosensitive chip and the circuit board in a wire bonding manner. The present application further provides a corresponding manufacturing method for a camera module and a photosensitive assembly. The present application can avoid or suppress the deformation of the photosensitive chip at a smaller cost of space size. The photosensitive assembly and the camera module of the present application can improve the structural strength of the circuit board. The photosensitive assembly and the camera module of the present application can improve the heat dissipation efficiency of the photosensitive chip.

A semiconductor device includes an array of flexible connectors configured to mitigate thermomechanical stresses. In one embodiment, a semiconductor assembly includes a substrate coupled to an array of flexible connectors. Each flexible connector can be transformed between a resting configuration and a loaded configuration. Each flexible connector includes a conductive wire electrically coupled to the substrate and a support material at least partially surrounding the conductive wire. The conductive wire has a first shape when the flexible connector is in the resting configuration and a second, different shape when the flexible connector is in the loaded configuration. The first shape includes at least two apices spaced apart from each other in a vertical dimension by a first distance, and the second shape includes the two apices spaced apart from each other in the vertical dimension by a second distance different than the first distance.