According to one embodiment, when a DSC curve is measured using a differential scanning calorimeter (DSC) for a brazing material for bonding a ceramic substrate and a metal plate, the brazing material has an endothermic peak within a range of not less than 550° C. and not more than 700° C. in a heating process. The brazing material favorably includes Ag, Cu, and Ti. The brazing material favorably has not less than two of the endothermic peaks within a range of not less than 550° C. and not more than 650° C. in the heating process.

Pastes are disclosed that are configured to coat a passage of a substrate. When the paste is sintered, the paste becomes electrically conductive so as to transmit electrical signals from a first end of the passage to ta second end of the passage that is opposite the first end of the passage. The metallized paste contains a lead-free glass frit, and has a coefficient of thermal expansion sufficiently matched to the substrate so as to avoid cracking of the sintered paste, the substrate, or both, during sintering.

A photosensitive glass paste contains a photosensitive organic component, and an inorganic component containing a glass powder and a ceramic filler. The glass powder contains a glass powder having a crystallization point. The difference between the crystallization point and the softening point of the glass powder having a crystallization point is from 85° C. to 180° C. The glass powder having a crystallization point is preferably a SiO.sub.2—B.sub.2O.sub.3—BaO—ZnO—Al.sub.2O.sub.3—MgO—La.sub.2O.sub.3 glass powder.

A multilayer ceramic substrate according to the present disclosure has ceramic layers and a patterned conductor, and a cavity is formed in the multilayer ceramic substrate. The cavity reaches to any one of principal surfaces of the multilayer ceramic substrate and forms an opening, and the opening is covered with a sealing member at the principal surface of the multilayer ceramic substrate.

A circuit formation method includes a wiring formation step of forming a wiring by applying a metal-containing liquid containing nanometer-sized metal fine particles onto a base and firing the metal-containing liquid, a paste application step of applying a resin paste containing micrometer-sized metal particles to be connected to the wiring formed in the wiring formation step, and a component placement step of placing a component having an electrode on the base, such that the electrode is in contact with the resin paste applied in the paste application step.

A wiring board includes an insulation substrate, a through-conductor, and a wiring conductor. The insulation substrate includes a first surface, a second surface opposite to the first surface, and a through-hole extending from the first surface to the second surface. The through-conductor is located in the through-hole and on an opening of the through-hole on a first surface side. The wiring conductor is located on the first surface and connected to the through-conductor. The through-conductor and the wiring conductor contain copper as a main component. The average size of Cu crystal grains in the through-conductor is larger than the average size of Cu crystal grains in the wiring conductor.

In a silicon nitride sintered body including silicon nitride crystal grains and a grain boundary phase, dislocation defect portions exists inside at least some of the silicon nitride crystal grains. A percentage of a number of the at least some of the silicon nitride crystal grains among any 50 of the silicon nitride crystal grains having completely visible contours in any cross section or surface of the silicon nitride sintered body is not less than 50% and not more than 100%. It is favorable that a plate thickness of the silicon nitride substrate, in which the silicon nitride sintered body is used, is within the range not less than 0.1 mm and not more than 0.4 mm. The TCT characteristics can be improved by using the silicon nitride substrate in the silicon nitride circuit board.

Proposed are a multilayer wiring board having both durability and chemical resistance, and a probe card including the same.

A substrate (1, 10) for electrical circuits, comprising at least one metal layer (2,3, 14) and a paper ceramic layer (11), which is joined face to face with the at least one metal layer (2,3, 14) and has a top side and bottom side (11a, 11b), wherein the paper ceramic layer (11) has a large number of cavities in the form of pores. Especially advantageously, the at least one metal layer (2, 3, 14) is connected to the paper ceramic layer (11) by means of at least one glue layer (6, 6a, 6b), which is produced by applying at least one glue (6a, 6a, 6b, 6b) to the metal layer (2,3, 14) and/or to the paper ceramic layer (11), wherein the cavities in the form of pores in the paper ceramic layer (11) are filled at least at the surface by means of the applied glue (6a, 6a, 6b,6b).

A multilayer ceramic substrate according to the present disclosure has ceramic layers and a patterned conductor, and a cavity is formed in the multilayer ceramic substrate. The cavity reaches to any one of principal surfaces of the multilayer ceramic substrate and forms an opening, and the opening is covered with a sealing member at the principal surface of the multilayer ceramic substrate.