Patent classifications
H05K2203/1163
METHODS OF ETCHING CONDUCTIVE FEATURES, AND RELATED DEVICES AND SYSTEMS
A method of making a device patterned with one or more electrically conductive features includes depositing a conductive material layer over an electrically insulating surface of a substrate, depositing an anti-corrosive material layer over the conductive material layer, and depositing an etch-resist material layer over the anti-corrosive material layer. The etch-resist material layer may be deposited over the anti-corrosive material layer, and the anti-corrosive material layer forming a bi-component etch mask in a pattern resulting in covered portions of the conductive material layer and exposed portions of the conductive material layer, the covered portions being positioned at locations corresponding to one or more conductive features of the device. A wet-etch process is performed to remove the exposed portions of the conductive material layer from the electrically insulating substrate, and the bi-component etch mask is removed to expose the remaining conductive material. Systems and devices relate to devices with patterned features.
FLEXIBLE CIRCUIT ELECTRODE ARRAY AND METHOD OF MANUFACTURING THE SAME
A method for manufacturing a flexible circuit electrode array, comprising: a) depositing a metal trace layer containing a base coating layer, a conducting layer and a top coating layer on the insulator polymer base layer; b) applying a layer of photoresist on the metal trace layer and patterning the metal trace layer and forming metal traces on the insulator polymer base layer; c) activating the insulator polymer base layer and depositing a top insulator polymer layer and forming one single insulating polymer layer with the base insulator polymer layer; d) applying a thin metal layer and a layer of photoresist on the surface of the insulator polymer layer and selective etching the insulator layer and the top coating layer to obtain at least one via; and e) filling the via with electrode material.
A layer of polymer is laid down. A layer of metal is applied to the polymer and patterned to create electrodes and leads for those electrodes. A second layer of polymer is applied over the metal layer and patterned to leave openings for the electrodes, or openings are created later by means such as laser ablation. Hence the array and its supply cable are formed of a single body. Alternatively, multiple alternating layers of metal and polymer may be applied to obtain more metal traces within a given width.
The method provides an excellent adhesion between the polymer base layer and the polymer top layer and insulation of the trace metals and electrodes.
Methods of etching conductive features, and related devices and systems
A method of making a device patterned with one or more electrically conductive features includes depositing a conductive material layer over an electrically insulating surface of a substrate, depositing an anti-corrosive material layer over the conductive material layer, and depositing an etch-resist material layer over the anti-corrosive material layer. The etch-resist material layer may be deposited over the anti-corrosive material layer, and the anti-corrosive material layer forming a bi-component etch mask in a pattern resulting in covered portions of the conductive material layer and exposed portions of the conductive material layer, the covered portions being positioned at locations corresponding to one or more conductive features of the device. A wet-etch process is performed to remove the exposed portions of the conductive material layer from the electrically insulating substrate, and the bi-component etch mask is removed to expose the remaining conductive material. Systems and devices relate to devices with patterned features.
Flexible circuit electrode array and method of manufacturing the same
A method for manufacturing a flexible circuit electrode array adapted to electrically communicate with organic tissue including the following steps: a) providing a flexible polymer base layer; b) curing the base layer; c) depositing a metal layer on base layer; d) patterning the metal layer and forming metal traces on the base layer; e) roughening the surface of the base layer; f) chemically reverting the cure of the surface of the base layer; g) depositing a flexible polymer top layer on the surface of the base layer and the metal traces; h) curing the top layer and the surface of the base layer forming one single flexible polymer layer; and i) creating openings through the single layer to the metal trace layer.
Reactively assisted ink for printed electronic circuits
An ink contains particles containing metal that reacts during sintering to produce an electrically conductive line or area having a diffusivity that is less than the diffusivity of the metal before the reaction. Resulting electronic circuits therefore exhibit longer useful lives, compared to conventionally inkjet printed circuits.
PRINTING OF NANOWIRE FILMS
Provided is a novel printing process for fabricating metallic, conductive and transparent ultra-thin nanowires and patterns including same on a substrate. The process includes two different controllable steps, each designed to achieving a useful and efficient pattern.
Offset conductive inks and compositions
The present invention is directed to energy curable offset conductive inks and hybrid offset conductive ink compositions that contain an oxidative curable ink and the energy curable offset conductive ink. The conductive inks and ink compositions exhibit low levels of resistance and hence have superior conductivity.
Reactively assisted ink for printed electronic circuits
An ink contains particles containing metal that reacts during sintering to produce an electrically conductive line or area having a diffusivity that is less than the diffusivity of the metal before the reaction. Resulting electronic circuits therefore exhibit longer useful lives, compared to conventionally inkjet printed circuits.
Semiconductor device having polyimide layer
Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.
METHOD FOR MAKING A CIRCUIT BOARD
A method for making a circuit board comprising: providing a silver clad laminate comprising a substrate and two silver foils; forming at least one through hole on the silver clad laminate, the through hole comprises an annular middle wall and two annular edge walls connected to two sides of the annular middle wall; forming an organic conductive film on the annular middle wall; forming a dry film pattern layer on the second area; plating copper to form a copper circuit layer on the first area, and to form a via hole in the through hole; removing the dry film pattern layer; and etching the second area of the silver foil away. The first area changes to a silver circuit layer. The copper circuit layer and the silver circuit layer define a conductive circuit layer. A circuit board made by the method is also provided.