A method of etching an electrically conductive layer structure during manufacturing a component carrier is provided. The method includes subjecting the electrically conductive layer structure to an etching composition having an etchant and a photosensitive compound to thereby form a recess in the electrically conductive layer structure; while, at least for a part of time, irradiating and/or heating the recess. In addition, an apparatus for etching an electrically conductive layer structure during manufacturing a component carrier, an etched electrically conductive layer structure and a component carrier are provided.

A carbene-coated metal foil is produced by applying an N-heterocyclic carbene (NHC) compound to one or more surfaces of a metal foil (e.g., an electrodeposited copper foil having a surface that is smooth and non-oxidized). The NHC compound contains a matrix-reactive pendant group that includes at least one of a vinyl-, allyl-, acrylic-, methacrylic-, styrenic-, amine-, amide- and epoxy-containing moiety capable of reacting with a base polymer (e.g., a vinyl-containing resin such as a polyphenylene oxide/triallyl-isocyanurate (PPO/TAIC) composition). The NHC compound may be synthesized by, for example, reacting a halogenated imidazolium salt (e.g., 1,3-bis(4-bromo-2,6-dimethylphenyl)-4,5-dihydro-1H-imidazol-3-ium chloride) and an organostannane having a vinyl-containing moiety (e.g., tributyl(vinyl)stannane) in the presence of a palladium catalyst. In some embodiments, an enhanced substrate for a printed circuit board (PCB) is produced by laminating the carbene-coated metal foil to a substrate that includes glass fiber impregnated with the base polymer.

A surface finish for a printed circuit board (PCB) and semiconductor wafer includes a nickel disposed over an aluminum or copper conductive metal surface. A barrier layer including all or fractions of a nitrogen-containing molecule is deposited on the surface of the nickel layer to make a barrier layer/electroless nickel (BLEN) surface finish. The barrier layer allows solder to be reflowed over the surface finish. Optionally, gold (e.g., immersion gold) may be coated over the barrier layer to create a nickel/barrier layer/gold (NBG) surface treatment. Presence of the barrier layer causes the surface treatment to be smoother than a conventional electroless nickel/immersion gold (ENIG) surface finish. Presence of the barrier layer causes a subsequently applied solder joint to be stronger and less subject to brittle failure than conventional ENIG.

Prior to electroless copper plating on substrates containing copper, an aqueous composition containing select imidazole compounds is applied to the substrate. The aqueous composition containing the select imidazole compounds counteract passivation of the copper on the substrate to improve the electroless copper plating process.

In an embodiment, a method of forming a stub-less via is provided. The method includes depositing a plurality of microcapsules containing a metal material in a via of a printed circuit board (PCB); rupturing the microcapsules and releasing the metal material; and sintering the metal material. In another embodiment, a method of forming a stub-less via is provided. The method includes forming a via in a printed circuit board (PCB); installing a plug in a portion of the via; depositing in the via a plurality of nanoparticles containing a metal material; and sintering the metal material.

A surface finish for a printed circuit board (PCB) and semiconductor wafer includes a nickel disposed over an aluminum or copper conductive metal surface. A barrier layer including all or fractions of a nitrogen-containing molecule is deposited on the surface of the nickel layer to make a barrier layer/electroless nickel (BLEN) surface finish. The barrier layer allows solder to be reflowed over the surface finish. Optionally, gold (e.g., immersion gold) may be coated over the barrier layer to create a nickel/barrier layer/gold (NBG) surface treatment. Presence of the barrier layer causes the surface treatment to be smoother than a conventional electroless nickel/immersion gold (ENIG) surface finish. Presence of the barrier layer causes a subsequently applied solder joint to be stronger and less subject to brittle failure than conventional ENIG.

A method of encapsulating an electronic assembly comprises disposing a plurality of electrically non-conductive particles on a substrate which carries one or more components of the electronic assembly; introducing a reactive parylene monomer in a vapor form into interstitial spaces among the plurality of the electrically non-conductive particles; and forming a parylene binder in the interstitial spaces of the electrically non-conductive particles from the reactive parylene monomer.

Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.

The present invention relates to a printing method comprising a step of printing a pattern on a substrate, preferably by ink jet printing, followed by a gold plating step by means of contact between the pre-printed pattern to be gold plated and a gold plating deposition device, such as a preferably conductive metal sheet, e.g. a multilayer film comprising a preferably conductive metal sheet.

The present invention provides a system and method for making a three-dimensional electronic, electromagnetic or electromechanical component/device by: (1) creating one or more layers of a three-dimensional substrate by depositing a substrate material in a layer-by-layer fashion, wherein the substrate includes a plurality of interconnection cavities and component cavities; (2) filling the interconnection cavities with a conductive material; and (3) placing one or more components in the component cavities.