A method for manufacturing a printed wiring board includes forming through holes in a double-sided copper-clad laminated plate such that a high-density region of the through holes and a low-density region of the through holes are formed, forming an electrolytic plating film on a copper foil of the plate in the high-density and low-density regions, forming a masking resist to mask the plating film in the high-density region, etching the plating film in the low-density region exposed from the resist such that the plating film in the low-density region is thinned, peeling off the resist from the plating film in the high-density region, and forming a conductor circuit including the copper foil and the plating film in the high-density and low-density regions. The forming of the plating film on the copper foil of the plate includes forming the plating film in the through holes in the high-density and low-density regions.

A component carrier and a method of manufacturing the component carrier are presented. The component carrier includes a stack with a plurality of electrically insulating layer structures and one or more electrically conductive layer structures, the one or more electrically conductive layer structures include two opposed conductive surfaces; a plurality of first vias, formed at a front side of the stack, the plurality of first vias are connected to one of the two opposed conductive surfaces through a respective first baseline-etch surface; and a plurality of second vias, formed at a back side of the stack, the front side is opposed to the back side, wherein the plurality of second vias is connected to the other one of the two opposed conductive surfaces through a respective second baseline-etch surface. The total area defined by the first baseline-etch surfaces is higher than the total area defined by the second baseline-etch surfaces and the depth of at least one of the first baseline-etch surfaces is lower than the depth of at least one of the second baseline-etch surfaces.

A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill vias during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a plug is inserted into each via and the plug is lowered to a depth just below a desired signal trace layer. A thin anti-electroplate coating is applied onto the walls of the via below the signal trace. Then the plugs are removed and a standard board plating process for the PCB is performed.

A method for forming a three-dimensional object with at least one conductive trace comprises providing an intermediate structure that is generated (e.g., additively or subtractively generated) from a first material in accordance with a model design of the three-dimensional object. The intermediate structure may have at least one predefined location for the at least one conductive trace. The model design includes the at least one predefined location. Next, the at least one conductive trace may be generated adjacent to the at least one predefined location of the intermediate structure. The at least one conductive trace may be formed of a second material that has an electrical and/or thermal conductivity that is greater than the first material.

According to various embodiments described herein, an article comprises a glass or glass-ceramic substrate having a first major surface and a second major surface opposite the first major surface, and a via extending through the substrate from the first major surface to the second major surface over an axial length in an axial direction. The article further comprises a helium hermetic adhesion layer disposed on the interior surface; and a metal connector disposed within the via, wherein the metal connector is adhered to the helium hermetic adhesion layer. The metal connector coats the interior surface of the via along the axial length of the via to define a first cavity from the first major surface to a first cavity length, the metal connector comprising a coating thickness of less than 12 m at the first major surface. Additionally, the metal connector coats the interior surface of the via along the axial length of the via to define a second cavity from the second major surface to a second cavity length, the metal connector comprising a coating thickness of less than 12 m at the second major surface and fully fills the via between the first cavity and the second cavity.

A method for constructing an external circuit structure is provided. The method is applied to an inner circuit substrate, wherein, the method comprises: laminating a copper foil and a prepreg on the inner circuit substrate; wherein, the prepreg is laminated between the copper foil and the inner circuit substrate; drilling at least one blind via from the copper foil to reach the copper circuit of the inner circuit substrate; removing smear generated in the at least one blind via during the drilling process; corroding off the copper foil; electroless copper plating on the prepreg to form an electroless plating copper layer on the prepreg; wherein, during the electroless copper plating process, a swelling process without desmearing process is implemented.

Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.

A method for filling a via on a printed circuit board formulates a paste as a dispersion of copper particulate that includes nanocopper particles in a solvent and a binder and depositing the paste into a via cavity formed in the printed circuit board. Heating the paste-filled cavity removes most of the solvent. The method sinters the deposited paste in the via cavity, planarizes the sintered via, and overplates the filled via with copper.

A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill vias during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a plug is inserted into each via and the plug is lowered to a depth just below a desired signal trace layer. A thin anti-electroplate coating is applied onto the walls of the via below the signal trace. Then the plugs are removed and a standard board plating process for the PCB is performed.

A method and structure are provided for implementing enhanced via creation without creating a via barrel stub. The need to backdrill vias during printed circuit board (PCB) manufacturing is eliminated. After the vias have been drilled, but before plating, a plug is inserted into each via and the plug is lowered to a depth just below a desired signal trace layer. A thin anti-electroplate coating is applied onto the walls of the via below the signal trace. Then the plugs are removed and a standard board plating process for the PCB is performed.