An insulation layer formation method comprises: a first step in which a surface treatment is applied to a base material to form thereon a high-resistance layer having high electric resistivity; a second step in which metal plating parts are formed on the base material that has undergone the first step in such a manner as to allow a high-resistance layer to be formed thereon; and a third process in which a high-resistance layer is formed on the base material that has undergone the second step.

The present disclosure relates to methods and apparatus for forming thin-form-factor reconstituted substrates and semiconductor device packages for radio frequency applications. The substrate and package structures described herein may be utilized in high-density 2D and 3D integrated devices for 4G, 5G, 6G, and other wireless network systems. In one embodiment, a silicon substrate is structured by laser ablation to include cavities for placement of semiconductor dies and vias for deposition of conductive interconnections. Additionally, one or more cavities are structured to be filled or occupied with a flowable dielectric material. Integration of one or more radio frequency components adjacent the dielectric-filled cavities enables improved performance of the radio frequency elements with reduced signal loss caused by the silicon substrate.

Embodiments include one or more air core inductors (ACIs) and a method of forming the ACIs. The ACI includes a first inductor loop on a substrate. The first inductor loop has a first line and a second line. The first line has a first thickness that is greater than a second thickness of the second line. The ACI also includes a dielectric over the substrate and the first and second lines. The first line has a top surface above a top surface of the second line. The ACI further includes a second inductor loop on the dielectric and the first inductor loop. The second inductor loop has is coupled to the top surface of the first line of the first inductor loop. The first inductor loop may also have a third thickness, where the third thickness is the distance between the top surfaces of the first and second line.

A multi-layer circuit board is formed multiple layers of a catalytic layer, each catalytic layer having an exclusion depth below a surface, where the cataltic particles are of sufficient density to provide electroless deposition in channels formed in the surface. A first catalytic layer has channels formed which are plated with electroless copper. Each subsequent catalytic layer is bonded or laminated to an underlying catalytic layer, a channel is formed which extends through the catalytic layer to an underlying electroless copper trace, and electroless copper is deposited into the channel to electrically connect with the underlying electroless copper trace. In this manner, traces may be formed which have a thickness greater than the thickness of a single catalytic layer.

Systems and methods for providing a soldered interface between a circuit board and a connector pin. The methods comprise: using a jet paste dispenser to apply first solder into a plated contact cavity formed in the circuit board; using a stencil screen printer to apply second solder (a) over the plated contact cavity which was at least partially filled with the first solder by the jet paste dispenser and (b) over at least a portion of a pad surrounding the plated contact cavity; inserting the connector pin in the plated contact cavity such that the connector pin passes through the second solder and extends at least partially through the first solder; and performing a reflow process to heat the first and second solder so as to create a solder joint between the circuit board and the connector pin.

A wiring board includes a conductor pattern formed on a board, and an insulating film that covers at least part of the conductor pattern. A first insulating film is provided in a first region on the board, the first region covering at least part of the conductor pattern and having a first border segment. A second insulating film is provided in a second region on the board, the second region covering at least part of the first region and having a second border segment. The second border segment is located outside the first region, and the shortest distance from any point belonging to the second border segment to the first border segment is not more than 400 μm.

A system and method for making vias in a laminated printed circuit board (PCB). A drill having both a mechanical drill and a laser drill is used to make the via. The mechanical drill is moved over a location in the PCB where a blind via is desired. The mechanical drill drills to a point where a tip of a bit of the mechanical drill is a predetermined distance above a target interconnect layer. Then the drill is moved such that the laser drill is located over the via where the mechanical drill had drilled the via. The laser drill then ablates the resin remaining above the target interconnect layer.

A method for protecting a substrate from corrosion, which method comprises in sequence: a first step including plasma polymerization of a precursor monomer and deposition of the resultant polymer onto at least one surface of a substrate; a second step including exposing the polymer to an inert gas in the presence of a plasma without further deposition of polymer onto the or each surface of the substrate; a third step including plasma polymerization of the precursor monomer used in the first step and deposition of the resultant polymer onto the polymer deposited in the first step so as to increase the thickness of the polymer; and optionally, a fourth step including exposing the polymer to an inert gas in the presence of a plasma without further deposition of polymer onto the or each surface of the substrate.

A component carrier includes a stack with at least one electrically conductive layer structure and a plurality of electrically insulating layer structure, a first component, a second component, a central core in which both the first component and the second component are embedded. A first electrically insulating structure encapsulates the first component. A second electrically insulating structure encapsulates the second component. The first component and the second component are electrically connected to an external electrically conductive structure through at least one electrically conductive contact passing through the first electrically insulating structure and/or the second electrically insulating structure.

A printed wiring board includes a base insulating layer, a conductor layer formed on the base insulating layer and including conductor pads, an underlayer formed on one of the conductor pads of the conductor layer and including a metal different from a metal of the conductor layer, a solder resist layer formed on the base insulating layer such that the solder resist layer is covering the conductor layer and has openings exposing the conductor pads, respectively, and a bump formed directly on a first conductor pad of the conductor pads and including a base plating layer formed in a first opening of the openings and a top plating layer formed on the base plating layer such that a metal of the base plating layer is same as the metal of the conductor layer.