A method for plating a printed circuit board, includes placing a substrate, including a through hole, in contact with a plating solution and disposing the substrate to face an electrode; and applying a pulsed current to each surface of the substrate, including applying pulsed currents of opposite polarity to both surfaces of the substrate at least once and applying pulsed forward currents to both surfaces of the substrate at least once, to plate from a middle to an end of the through hole.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

A method for manufacturing a semiconductor device, for example formed utilizing component stacking. As non-limiting examples, various aspects of this disclosure provide a method for reducing warpage and/or stress in stacked semiconductor devices.

A method of etching an electrically conductive layer structure during manufacturing a component carrier is provided. The method includes carrying out a first etching of at least one exposed region of an electrically conductive layer structure by a first etching composition having a photo-hardenable compound to thereby form a recess in the electrically conductive layer structure, hardening the photo-hardenable compound by irradiation with photons selectively on an upper side wall portion of the recess to thereby cover the upper side wall portion with a photo-hardened compound, carrying out a second etching by a second etching composition selectively on a side wall portion and/or bottom portion of the recess being not covered with the photo-hardened compound, and subsequently removing the photo-hardened compound from the side wall portion. In addition, a component carrier is provided.

The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

Low temperature processes for converting mixtures of metal inks into alloys. The alloys can be dealloyed by etching. A method comprising: depositing at least one precursor composition on at least one substrate to form at least one deposited structure, wherein the precursor composition comprises at least two metal complexes, including at least one first metal complex comprising at least one first metal and at least one second metal complex different from the first metal complex and comprising at least one second metal different from the first metal, treating the deposited structure so that the first metal and the second metal become elemental forms of the first metal and the second metal in a treated structure. Further, one can remove at least some of the first metal to leave a nanoporous material comprising at least the second metal. Precursor compositions can be formulated to be homogeneous compositions.

Disclosed herein are implementations of methods and devices for stacking printed circuit board (PCB) assemblies (PCBA) with a single reflow process which decreases impact on surface mount technology (SMT) component and solder joint reliability. A method includes transferring solder paste on to a bottom PCB and forming a bottom PCBA by placing SMT components on the bottom PCB. A middle PCB is stacked on the bottom PCBA and solder paste is transferred on to the middle PCB. A top PCB is stacked on the middle PCB and solder paste is transferred on to the top PCB. SMT components are placed on the top PCB to form a stacked assembly. The stacked assembly is reflowed in a single reflow so that all solder paste simultaneously or nearly simultaneously melts to bond SMT components to respective PCB boards and to bond respective PCBs to each other.

The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.