Provided is photo-sintering nano ink. The photo-sintering nano ink includes a photo-sintering precursor including a conductive nano particle and an oxide film surrounding the conductive nano particle, polymer binder resin, and an adhesive.

A method for plating a printed circuit board, includes placing a substrate, including a through hole, in contact with a plating solution and disposing the substrate to face an electrode; and applying a pulsed current to each surface of the substrate, including applying pulsed currents of opposite polarity to both surfaces of the substrate at least once and applying pulsed forward currents to both surfaces of the substrate at least once, to plate from a middle to an end of the through hole.

A printed circuit board includes a substrate having a first surface and a second surface, opposite to the first surface, and having a through-portion penetrating between the first surface and the second surface; and a through-via disposed in at least a portion of the through-portion, wherein the through-via includes a first metal layer having a first groove portion facing an interior of the through-portion from the first surface of the substrate and a second groove portion facing the interior of the through-portion from the second surface of the substrate, and the first metal layer has a first region, and a second region, having different average grain sizes.

A method for manufacturing includes coating a substrate (22) with a matrix (28) containing a material to be patterned on the substrate. A pattern is fixed in the matrix by directing a pulsed energy beam to impinge on a locus of the pattern so as to cause adhesion of the material to the substrate along the pattern without fully sintering the material in the pattern. The matrix remaining on the substrate outside the fixed pattern is removed, and after removing the matrix, the material in the pattern is sintered.

A plater arrangement for filling a hole formed in a component carrier with copper is disclosed. The plater arrangement includes an electroless plater section for forming a layer of an electrically conductive material, which layer covers at least part of a surface of a wall of a component carrier and where the wall delimits the hole in the component carrier and an electro-plater section for covering at least partially the layer and filling at least partially an unfilled volume of the hole with copper by an electro-plating process, wherein at least partially covering the layer and at least partially filling the hole is done by flash-plating. The electro-plater section having a bath for plating with copper.

A method of copper electroplating in the manufacture of printed circuit boards. The method is used for filling through-holes and blind micro-vias with copper. The method includes the steps of: (1) preparing an electronic substrate to. receive copper electroplating thereon: (2) forming at least one of one or more through-holes and/or one or more blind micro-vias in the electronic substrate; and (3) electroplating copper in the at one or more through-holes and/or one or more blind micro-vias by contacting the electronic substrate with an acid copper electrolyte. The acid copper electrolyte is used to plate the one or more through-holes and/or the one or more blind micro-vias using a complex waveform including pulse reverse plating. DC plating and/or synchronous pulse plating. The complex waveforms can be used for filling through-holes and blind microvias with copper without defects.

The present invention refers to a method of preparing a high density interconnect printed circuit board (HDI PCB) including microvias filled with copper comprising the steps of: a1) providing a multi-layer substrate comprising (i) a stack assembly of an electrically conductive interlayer embedded between two insulating layers, (ii) a cover layer, and (iii) a microvia extending from the peripheral surface and ending on the conductive interlayer; b1) depositing a conductive layer; or a2) providing a multi-layer substrate comprising (i) a stack assembly of an electrically conductive interlayer embedded between two insulating layers, (ii) a microvia extending from the peripheral surface and ending on the conductive interlayer; b2) depositing a conductive layer; and c) electrodepositing a copper filling in the microvia and a first copper layer on the conductive layer which form together a planar surface and the thickness of the first copper layer is from 0.1 to 3 ?m.

Pulse plating methods which include a forward pulse but no reverse pulse inhibit or reduce dimpling and voids during copper electroplating of through-holes in substrates such as printed circuit boards. The pulse plating methods may be used to fill through-holes with copper where the through-holes are coated with electroless copper or flash copper.

The present invention refers to a method of preparing a high density interconnect printed circuit board (HDI PCB) or IC substrates including through-holes and/or grate structures filled with copper, which comprises the steps of: a) providing a multi-layer substrate; b) forming a non-copper conductive layer or a copper layer on the cover layer and on an inner surface of the through-hole, respectively on an inner surface of the grate structure; c) forming a patterned masking film; d) electrodepositing copper; e) removing the masking film; and f) electrodepositing a copper filling.

The present invention is a method for manufacturing a multilayer wiring board having (1) a step of providing with a hole for a via hole from a metal foil for an upper layer wiring pattern to an inner layer wiring pattern by using a conformal method or a direct laser method, and (2) a step of forming a via hole by forming electrolytic filling plating layers in the hole for a via hole, wherein the formation of the electrolytic filling plating layers in the step (2) is carried out by repeating change in electric current density of temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating and then increasing it again, two or more times before the electrolytic filling plating layers block an opening of the hole for a via hole.